1 /* 2 * Copyright (c) 2024 Analog Devices Inc. 3 * Copyright (c) 2024 Baylibre SAS 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_GPIO_GPIO_MAX14906_H_ 9 #define ZEPHYR_DRIVERS_GPIO_GPIO_MAX14906_H_ 10 11 #define MAX14906_FAULT2_ENABLES 5 12 #define MAX14906_CHANNELS 4 13 #define MAX14916_CHANNELS 8 14 #define MAX149x6_MAX_PKT_SIZE 3 15 16 #define MAX14906_SETOUT_REG 0x0 17 #define MAX14906_SETLED_REG 0x1 18 #define MAX14906_DOILEVEL_REG 0x2 19 #define MAX14906_INT_REG 0x3 20 #define MAX14906_OVR_LD_REG 0x4 21 #define MAX14906_OPN_WIR_FLT_REG 0x5 22 #define MAX14906_SHT_VDD_FLT_REG 0x6 23 #define MAX14906_GLOB_ERR_REG 0x7 24 #define MAX14906_OPN_WR_EN_REG 0x8 25 #define MAX14906_SHT_VDD_EN_REG 0x9 26 #define MAX14906_CONFIG1_REG 0xA 27 #define MAX14906_CONFIG2_REG 0xB 28 #define MAX14906_CONFIG_DI_REG 0xC 29 #define MAX14906_CONFIG_DO_REG 0xD 30 #define MAX14906_CONFIG_CURR_LIM 0xE 31 #define MAX14906_CONFIG_MASK 0xF 32 33 #define MAX149x6_CHIP_ADDR_MASK GENMASK(7, 6) 34 #define MAX149x6_ADDR_MASK GENMASK(4, 1) 35 #define MAX149x6_RW_MASK BIT(0) 36 37 /* DoiLevel register */ 38 #define MAX14906_DOI_LEVEL_MASK(x) BIT(x) 39 40 /* SetOUT register */ 41 #define MAX14906_HIGHO_MASK(x) BIT(x) 42 43 #define MAX14906_DO_MASK(x) (GENMASK(1, 0) << (2 * (x))) 44 #define MAX14906_CH_DIR_MASK(x) BIT((x) + 4) 45 #define MAX14906_CH(x) (x) 46 #define MAX14906_IEC_TYPE_MASK BIT(7) 47 #define MAX14906_CL_MASK(x) (GENMASK(1, 0) << (2 * (x))) 48 49 /** 50 * @brief Hardwired device address 51 */ 52 enum max149x6_spi_addr { 53 MAX14906_ADDR_0, /* A0=0, A1=0 */ 54 MAX14906_ADDR_1, /* A0=1, A1=0 */ 55 MAX14906_ADDR_2, /* A0=0, A1=1 */ 56 MAX14906_ADDR_3, /* A0=1, A1=1 */ 57 }; 58 59 enum max14906_iec_type { 60 MAX14906_TYPE_1_3, 61 MAX14906_TYPE_2, 62 }; 63 64 /** 65 * @brief Channel configuration options. 66 */ 67 enum max14906_function { 68 MAX14906_OUT, 69 MAX14906_IN, 70 MAX14906_HIGH_Z 71 }; 72 73 /** 74 * @brief Configuration options for the output driver (on each channel). 75 */ 76 enum max14906_do_mode { 77 MAX14906_HIGH_SIDE, 78 MAX14906_HIGH_SIDE_INRUSH, 79 MAX14906_PUSH_PULL_CLAMP, 80 MAX14906_PUSH_PULL 81 }; 82 83 /** 84 * @brief Current limit options for output channels. 85 */ 86 enum max14906_cl { 87 MAX14906_CL_600, 88 MAX14906_CL_130, 89 MAX14906_CL_300, 90 MAX14906_CL_1200, 91 }; 92 93 union max14906_doi_level { 94 uint8_t reg_raw; 95 struct { 96 uint8_t VDDOK_FAULT1: 1; /* BIT0 */ 97 uint8_t VDDOK_FAULT2: 1; 98 uint8_t VDDOK_FAULT3: 1; 99 uint8_t VDDOK_FAULT4: 1; 100 uint8_t SAFE_DAMAGE_F1: 1; 101 uint8_t SAFE_DAMAGE_F2: 1; 102 uint8_t SAFE_DAMAGE_F3: 1; 103 uint8_t SAFE_DAMAGE_F4: 1; /* BIT7 */ 104 } reg_bits; 105 }; 106 107 union max14906_interrupt { 108 uint8_t reg_raw; 109 struct { 110 uint8_t OVER_LD_FAULT: 1; /* BIT0 */ 111 uint8_t CURR_LIM: 1; 112 uint8_t OW_OFF_FAULT: 1; 113 uint8_t ABOVE_VDD_FAULT: 1; 114 uint8_t SHT_VDD_FAULT: 1; 115 uint8_t DE_MAG_FAULT: 1; 116 uint8_t SUPPLY_ERR: 1; 117 uint8_t COM_ERR: 1; /* BIT7 */ 118 } reg_bits; 119 }; 120 121 union max14906_ovr_ld_chf { 122 uint8_t reg_raw; 123 struct { 124 uint8_t OVL1: 1; /* BIT0 */ 125 uint8_t OVL2: 1; 126 uint8_t OVL3: 1; 127 uint8_t OVL4: 1; 128 uint8_t CL1: 1; 129 uint8_t CL2: 1; 130 uint8_t CL3: 1; 131 uint8_t CL4: 1; /* BIT7 */ 132 } reg_bits; 133 }; 134 135 union max14906_opn_wir_chf { 136 uint8_t reg_raw; 137 struct { 138 uint8_t OW_OFF1: 1; /* BIT0 */ 139 uint8_t OW_OFF2: 1; 140 uint8_t OW_OFF3: 1; 141 uint8_t OW_OFF4: 1; 142 uint8_t ABOVE_VDD1: 1; 143 uint8_t ABOVE_VDD2: 1; 144 uint8_t ABOVE_VDD3: 1; 145 uint8_t ABOVE_VDD4: 1; /* BIT7 */ 146 } reg_bits; 147 }; 148 149 union max14906_sht_vdd_chf { 150 uint8_t reg_raw; 151 struct { 152 uint8_t SHVDD1: 1; /* BIT0 */ 153 uint8_t SHVDD2: 1; 154 uint8_t SHVDD3: 1; 155 uint8_t SHVDD4: 1; 156 uint8_t VDDOV1: 1; 157 uint8_t VDDOV2: 1; 158 uint8_t VDDOV3: 1; 159 uint8_t VDDOV4: 1; /* BIT7 */ 160 } reg_bits; 161 }; 162 163 union max14906_global_err { 164 uint8_t reg_raw; 165 struct { 166 uint8_t VINT_UV: 1; /* BIT0 */ 167 uint8_t V5_UVLO: 1; 168 uint8_t VDD_LOW: 1; 169 uint8_t VDD_WARN: 1; 170 uint8_t VDD_UVLO: 1; 171 uint8_t THRMSHUTD: 1; 172 uint8_t LOSSGND: 1; 173 uint8_t WDOG_ERR: 1; /* BIT7 */ 174 } reg_bits; 175 }; 176 177 union max14906_opn_wr_en { 178 uint8_t reg_raw; 179 struct { 180 uint8_t OW_OFF_EN1: 1; /* BIT0 */ 181 uint8_t OW_OFF_EN2: 1; 182 uint8_t OW_OFF_EN3: 1; 183 uint8_t OW_OFF_EN4: 1; 184 uint8_t GDRV_EN1: 1; 185 uint8_t GDRV_EN2: 1; 186 uint8_t GDRV_EN3: 1; 187 uint8_t GDRV_EN4: 1; /* BIT7 */ 188 } reg_bits; 189 }; 190 191 union max14906_sht_vdd_en { 192 uint8_t reg_raw; 193 struct { 194 uint8_t SH_VDD_EN1: 1; /* BIT0 */ 195 uint8_t SH_VDD_EN2: 1; 196 uint8_t SH_VDD_EN3: 1; 197 uint8_t SH_VDD_EN4: 1; 198 uint8_t VDD_OV_EN1: 1; 199 uint8_t VDD_OV_EN2: 1; 200 uint8_t VDD_OV_EN3: 1; 201 uint8_t VDD_OV_EN4: 1; /* BIT7 */ 202 } reg_bits; 203 }; 204 205 union max14906_config_di { 206 uint8_t reg_raw; 207 struct { 208 uint8_t OVL_BLANK: 2; /* BIT0 */ 209 uint8_t OVL_STRETCH_EN: 1; 210 uint8_t ABOVE_VDD_PROT_EN: 1; 211 uint8_t VDD_FAULT_SEL: 1; 212 uint8_t VDD_FAULT_DIS: 1; 213 uint8_t RESERVED: 1; 214 uint8_t TYP_2_DI: 1; /* BIT7 */ 215 } reg_bits; 216 }; 217 218 union max14906_config_do { 219 uint8_t reg_raw; 220 struct { 221 uint8_t DO_MODE1: 2; /* BIT0 */ 222 uint8_t DO_MODE2: 2; 223 uint8_t DO_MODE3: 2; 224 uint8_t DO_MODE4: 2; /* BIT7 */ 225 } reg_bits; 226 }; 227 228 union max14906_config_curr_lim { 229 uint8_t reg_raw; 230 struct { 231 uint8_t CL1: 2; /* BIT0 */ 232 uint8_t CL2: 2; 233 uint8_t CL3: 2; 234 uint8_t CL4: 2; /* BIT7 */ 235 } reg_bits; 236 }; 237 238 union max14906_mask { 239 uint8_t reg_raw; 240 struct { 241 uint8_t OVER_LD_M: 1; /* BIT0 */ 242 uint8_t CURR_LIM_M: 1; 243 uint8_t OW_OFF_M: 1; 244 uint8_t ABOVE_VDD_M: 1; 245 uint8_t SHT_VDD_M: 1; 246 uint8_t VDD_OK_M: 1; 247 uint8_t SUPPLY_ERR_M: 1; 248 uint8_t COM_ERR_M: 1; /* BIT7 */ 249 } reg_bits; 250 }; 251 252 union max14906_config1 { 253 uint8_t reg_raw; 254 struct { 255 uint8_t FLED_SET: 1; /* BIT0 */ 256 uint8_t SLED_SET: 1; 257 uint8_t FLED_STRETCH: 2; 258 uint8_t FFILTER_EN: 1; 259 uint8_t FILTER_LONG: 1; 260 uint8_t FLATCH_EN: 1; 261 uint8_t LED_CURR_LIM: 1; /* BIT7 */ 262 } reg_bits; 263 }; 264 265 union max14906_config2 { 266 uint8_t reg_raw; 267 struct { 268 uint8_t VDD_ON_THR: 1; /* BIT0 */ 269 uint8_t SYNCH_WD_EN: 1; 270 uint8_t SHT_VDD_THR: 2; 271 uint8_t OW_OFF_CS: 2; 272 uint8_t WD_TO: 2; /* BIT7 */ 273 } reg_bits; 274 }; 275 276 /* Config1 register Enable/Disable SLED */ 277 #define MAX149x6_SLED_MASK BIT(1) 278 /* Config1 register Enable/Disable FLED */ 279 #define MAX149x6_FLED_MASK BIT(0) 280 281 #define MAX149x6_ENABLE 1 282 #define MAX149x6_DISABLE 0 283 284 struct max149x6_config { 285 struct spi_dt_spec spi; 286 struct gpio_dt_spec fault_gpio; 287 struct gpio_dt_spec ready_gpio; 288 struct gpio_dt_spec sync_gpio; 289 struct gpio_dt_spec en_gpio; 290 bool crc_en; 291 union max14906_config1 config1; 292 union max14906_config2 config2; 293 union max14906_config_curr_lim curr_lim; 294 union max14906_config_di config_do; 295 union max14906_config_do config_di; 296 enum max149x6_spi_addr spi_addr; 297 uint8_t pkt_size; 298 }; 299 300 #define max14906_config max149x6_config 301 302 struct max14906_data { 303 struct gpio_driver_data common; 304 struct { 305 union max14906_doi_level doi_level; 306 union max14906_ovr_ld_chf ovr_ld; 307 union max14906_opn_wir_chf opn_wir; 308 union max14906_sht_vdd_chf sht_vdd; 309 } chan; 310 struct { 311 union max14906_opn_wr_en opn_wr_en; 312 union max14906_sht_vdd_en sht_vdd_en; 313 } chan_en; 314 struct { 315 union max14906_interrupt interrupt; 316 union max14906_global_err glob_err; 317 union max14906_mask mask; 318 } glob; 319 }; 320 321 #endif 322
