1 /*
2 * Copyright (c) 2024, Ambiq Micro Inc. <www.ambiq.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT mspi_atxp032
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/pm/device.h>
11 #include <zephyr/logging/log.h>
12 #include <zephyr/sys/util.h>
13 #include <zephyr/drivers/gpio.h>
14 #include <zephyr/drivers/mspi.h>
15 #if CONFIG_SOC_FAMILY_AMBIQ
16 #include "mspi_ambiq.h"
17 typedef struct mspi_ambiq_timing_cfg mspi_timing_cfg;
18 typedef enum mspi_ambiq_timing_param mspi_timing_param;
19
20 #else
21 typedef struct mspi_timing_cfg mspi_timing_cfg;
22 typedef enum mspi_timing_param mspi_timing_param;
23 #define TIMING_CFG_GET_RX_DUMMY(cfg)
24 #define TIMING_CFG_SET_RX_DUMMY(cfg, num)
25 #endif
26
27 #include <zephyr/drivers/flash.h>
28 #include "spi_nor.h"
29 LOG_MODULE_REGISTER(flash_mspi_atxp032, CONFIG_FLASH_LOG_LEVEL);
30
31 #define NOR_WRITE_SIZE 1
32 #define NOR_ERASE_VALUE 0xff
33
34 #define ATXP032_VENDOR_ID 0x43
35
36 enum atxp032_dummy_clock {
37 ATXP032_DC_8,
38 ATXP032_DC_10,
39 ATXP032_DC_12,
40 ATXP032_DC_14,
41 ATXP032_DC_16,
42 ATXP032_DC_18,
43 ATXP032_DC_20,
44 ATXP032_DC_22,
45 };
46 struct flash_mspi_atxp032_config {
47 uint32_t port;
48 uint32_t mem_size;
49 struct flash_parameters flash_param;
50 struct flash_pages_layout page_layout;
51
52 const struct device *bus;
53 struct mspi_dev_id dev_id;
54 struct mspi_dev_cfg serial_cfg;
55 struct mspi_dev_cfg tar_dev_cfg;
56 struct mspi_xip_cfg tar_xip_cfg;
57 struct mspi_scramble_cfg tar_scramble_cfg;
58
59 mspi_timing_cfg tar_timing_cfg;
60 mspi_timing_param timing_cfg_mask;
61
62 bool sw_multi_periph;
63 };
64
65 struct flash_mspi_atxp032_data {
66 struct mspi_dev_cfg dev_cfg;
67 struct mspi_xip_cfg xip_cfg;
68 struct mspi_scramble_cfg scramble_cfg;
69 mspi_timing_cfg timing_cfg;
70 struct mspi_xfer trans;
71 struct mspi_xfer_packet packet;
72
73 struct k_sem lock;
74 uint32_t jedec_id;
75 };
76
atxp032_get_dummy_clk(uint8_t rxdummy,uint32_t * dummy_clk)77 static int atxp032_get_dummy_clk(uint8_t rxdummy, uint32_t *dummy_clk)
78 {
79 switch (rxdummy) {
80 case 8:
81 *dummy_clk = ATXP032_DC_8;
82 break;
83 case 10:
84 *dummy_clk = ATXP032_DC_10;
85 break;
86 case 12:
87 *dummy_clk = ATXP032_DC_12;
88 break;
89 case 14:
90 *dummy_clk = ATXP032_DC_14;
91 break;
92 case 16:
93 *dummy_clk = ATXP032_DC_16;
94 break;
95 case 18:
96 *dummy_clk = ATXP032_DC_18;
97 break;
98 case 20:
99 *dummy_clk = ATXP032_DC_20;
100 break;
101 case 22:
102 *dummy_clk = ATXP032_DC_22;
103 break;
104 default:
105 return 1;
106 }
107 return 0;
108 }
109
flash_mspi_atxp032_command_write(const struct device * flash,uint8_t cmd,uint32_t addr,uint16_t addr_len,uint32_t tx_dummy,uint8_t * wdata,uint32_t length)110 static int flash_mspi_atxp032_command_write(const struct device *flash, uint8_t cmd, uint32_t addr,
111 uint16_t addr_len, uint32_t tx_dummy, uint8_t *wdata,
112 uint32_t length)
113 {
114 const struct flash_mspi_atxp032_config *cfg = flash->config;
115 struct flash_mspi_atxp032_data *data = flash->data;
116 int ret;
117
118 data->packet.dir = MSPI_TX;
119 data->packet.cmd = cmd;
120 data->packet.address = addr;
121 data->packet.data_buf = wdata;
122 data->packet.num_bytes = length;
123
124 data->trans.async = false;
125 data->trans.xfer_mode = MSPI_PIO;
126 data->trans.tx_dummy = tx_dummy;
127 data->trans.cmd_length = 1;
128 data->trans.addr_length = addr_len;
129 data->trans.hold_ce = false;
130 data->trans.packets = &data->packet;
131 data->trans.num_packet = 1;
132 data->trans.timeout = 10;
133
134 ret = mspi_transceive(cfg->bus, &cfg->dev_id, (const struct mspi_xfer *)&data->trans);
135 if (ret) {
136 LOG_ERR("MSPI write transaction failed with code: %d/%u", ret, __LINE__);
137 return -EIO;
138 }
139 return ret;
140 }
141
flash_mspi_atxp032_command_read(const struct device * flash,uint8_t cmd,uint32_t addr,uint16_t addr_len,uint32_t rx_dummy,uint8_t * rdata,uint32_t length)142 static int flash_mspi_atxp032_command_read(const struct device *flash, uint8_t cmd, uint32_t addr,
143 uint16_t addr_len, uint32_t rx_dummy, uint8_t *rdata,
144 uint32_t length)
145 {
146 const struct flash_mspi_atxp032_config *cfg = flash->config;
147 struct flash_mspi_atxp032_data *data = flash->data;
148 int ret;
149
150 data->packet.dir = MSPI_RX;
151 data->packet.cmd = cmd;
152 data->packet.address = addr;
153 data->packet.data_buf = rdata;
154 data->packet.num_bytes = length;
155
156 data->trans.async = false;
157 data->trans.xfer_mode = MSPI_PIO;
158 data->trans.rx_dummy = rx_dummy;
159 data->trans.cmd_length = 1;
160 data->trans.addr_length = addr_len;
161 data->trans.hold_ce = false;
162 data->trans.packets = &data->packet;
163 data->trans.num_packet = 1;
164 data->trans.timeout = 10;
165
166 ret = mspi_transceive(cfg->bus, &cfg->dev_id, (const struct mspi_xfer *)&data->trans);
167 if (ret) {
168 LOG_ERR("MSPI read transaction failed with code: %d/%u", ret, __LINE__);
169 return -EIO;
170 }
171 return ret;
172 }
173
acquire(const struct device * flash)174 static void acquire(const struct device *flash)
175 {
176 const struct flash_mspi_atxp032_config *cfg = flash->config;
177 struct flash_mspi_atxp032_data *data = flash->data;
178
179 k_sem_take(&data->lock, K_FOREVER);
180
181 if (cfg->sw_multi_periph) {
182 while (mspi_dev_config(cfg->bus, &cfg->dev_id,
183 MSPI_DEVICE_CONFIG_ALL, &data->dev_cfg)) {
184 ;
185 }
186 } else {
187 while (mspi_dev_config(cfg->bus, &cfg->dev_id,
188 MSPI_DEVICE_CONFIG_NONE, NULL)) {
189 ;
190 }
191 }
192 }
193
release(const struct device * flash)194 static void release(const struct device *flash)
195 {
196 const struct flash_mspi_atxp032_config *cfg = flash->config;
197 struct flash_mspi_atxp032_data *data = flash->data;
198
199 while (mspi_get_channel_status(cfg->bus, cfg->port)) {
200 ;
201 }
202
203 k_sem_give(&data->lock);
204 }
205
flash_mspi_atxp032_write_enable(const struct device * flash)206 static int flash_mspi_atxp032_write_enable(const struct device *flash)
207 {
208 int ret;
209
210 LOG_DBG("Enabling write");
211 ret = flash_mspi_atxp032_command_write(flash, SPI_NOR_CMD_WREN, 0, 0, 0, NULL, 0);
212
213 return ret;
214 }
215
flash_mspi_atxp032_write_disable(const struct device * flash)216 static int flash_mspi_atxp032_write_disable(const struct device *flash)
217 {
218 int ret;
219
220 LOG_DBG("Disabling write");
221 ret = flash_mspi_atxp032_command_write(flash, SPI_NOR_CMD_WRDI, 0, 0, 0, NULL, 0);
222
223 return ret;
224 }
225
flash_mspi_atxp032_reset(const struct device * flash)226 static int flash_mspi_atxp032_reset(const struct device *flash)
227 {
228 int ret;
229
230 ret = flash_mspi_atxp032_write_enable(flash);
231 if (ret) {
232 return ret;
233 }
234
235 LOG_DBG("Return to SPI mode");
236 ret = flash_mspi_atxp032_command_write(flash, 0xFF, 0, 0, 0, NULL, 0);
237 if (ret) {
238 return ret;
239 }
240
241 ret = flash_mspi_atxp032_write_disable(flash);
242 if (ret) {
243 return ret;
244 }
245
246 return ret;
247 }
248
flash_mspi_atxp032_get_vendor_id(const struct device * flash,uint8_t * vendor_id)249 static int flash_mspi_atxp032_get_vendor_id(const struct device *flash, uint8_t *vendor_id)
250 {
251 struct flash_mspi_atxp032_data *data = flash->data;
252 uint8_t buffer[11];
253 int ret;
254
255 if (vendor_id == NULL) {
256 return -EINVAL;
257 }
258
259 LOG_DBG("Reading id");
260 /* serial mode */
261 ret = flash_mspi_atxp032_command_read(flash, SPI_NOR_CMD_RDID, 0, 0, 0, buffer, 11);
262 *vendor_id = buffer[7];
263
264 data->jedec_id = (buffer[7] << 16) | (buffer[8] << 8) | buffer[9];
265
266 return ret;
267 }
268
flash_mspi_atxp032_unprotect_sector(const struct device * flash,off_t addr)269 static int flash_mspi_atxp032_unprotect_sector(const struct device *flash, off_t addr)
270 {
271 int ret;
272
273 LOG_DBG("unprotect sector at 0x%08zx", (ssize_t)addr);
274
275 ret = flash_mspi_atxp032_command_write(flash, 0x39, addr, 4, 0, NULL, 0);
276
277 return ret;
278 }
279
flash_mspi_atxp032_erase_sector(const struct device * flash,off_t addr)280 static int flash_mspi_atxp032_erase_sector(const struct device *flash, off_t addr)
281 {
282 int ret;
283
284 LOG_DBG("Erasing sector at 0x%08zx", (ssize_t)addr);
285
286 ret = flash_mspi_atxp032_command_write(flash, SPI_NOR_CMD_SE, addr, 4, 0, NULL, 0);
287
288 return ret;
289 }
290
flash_mspi_atxp032_erase_block(const struct device * flash,off_t addr)291 static int flash_mspi_atxp032_erase_block(const struct device *flash, off_t addr)
292 {
293 int ret;
294
295 LOG_DBG("Erasing block at 0x%08zx", (ssize_t)addr);
296
297 ret = flash_mspi_atxp032_command_write(flash, SPI_NOR_CMD_BE, addr, 4, 0, NULL, 0);
298
299 return ret;
300 }
301
flash_mspi_atxp032_erase_chip(const struct device * flash)302 static int flash_mspi_atxp032_erase_chip(const struct device *flash)
303 {
304 int ret;
305
306 LOG_DBG("Erasing chip");
307
308 ret = flash_mspi_atxp032_command_write(flash, SPI_NOR_CMD_CE, 0, 0, 0, NULL, 0);
309
310 return ret;
311 }
312
flash_mspi_atxp032_page_program(const struct device * flash,off_t offset,void * wdata,size_t len)313 static int flash_mspi_atxp032_page_program(const struct device *flash, off_t offset, void *wdata,
314 size_t len)
315 {
316 const struct flash_mspi_atxp032_config *cfg = flash->config;
317 struct flash_mspi_atxp032_data *data = flash->data;
318 int ret;
319
320 data->packet.dir = MSPI_TX;
321 data->packet.cmd = data->dev_cfg.write_cmd;
322 data->packet.address = offset;
323 data->packet.data_buf = wdata;
324 data->packet.num_bytes = len;
325
326 data->trans.async = false;
327 data->trans.xfer_mode = MSPI_DMA;
328 data->trans.tx_dummy = data->dev_cfg.tx_dummy;
329 data->trans.cmd_length = data->dev_cfg.cmd_length;
330 data->trans.addr_length = data->dev_cfg.addr_length;
331 data->trans.hold_ce = false;
332 data->trans.priority = 1;
333 data->trans.packets = &data->packet;
334 data->trans.num_packet = 1;
335 data->trans.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE;
336
337 LOG_DBG("Page programming %d bytes to 0x%08zx", len, (ssize_t)offset);
338
339 ret = mspi_transceive(cfg->bus, &cfg->dev_id, (const struct mspi_xfer *)&data->trans);
340 if (ret) {
341 LOG_ERR("MSPI write transaction failed with code: %d/%u", ret, __LINE__);
342 return -EIO;
343 }
344 return ret;
345 }
346
flash_mspi_atxp032_busy_wait(const struct device * flash)347 static int flash_mspi_atxp032_busy_wait(const struct device *flash)
348 {
349 const struct flash_mspi_atxp032_config *cfg = flash->config;
350 struct flash_mspi_atxp032_data *data = flash->data;
351 mspi_timing_cfg bkp = data->timing_cfg;
352
353 uint32_t status = 0;
354 uint32_t rx_dummy;
355 int ret;
356
357 if (data->dev_cfg.io_mode == MSPI_IO_MODE_SINGLE) {
358 rx_dummy = 0;
359 } else {
360 rx_dummy = 4;
361 TIMING_CFG_SET_RX_DUMMY(&data->timing_cfg, 4);
362 if (mspi_timing_config(cfg->bus, &cfg->dev_id, cfg->timing_cfg_mask,
363 (void *)&data->timing_cfg)) {
364 LOG_ERR("Failed to config mspi controller/%u", __LINE__);
365 return -EIO;
366 }
367 }
368
369 do {
370 LOG_DBG("Reading status register");
371 ret = flash_mspi_atxp032_command_read(flash, SPI_NOR_CMD_RDSR, 0, 0, rx_dummy,
372 (uint8_t *)&status, 1);
373 if (ret) {
374 LOG_ERR("Could not read status");
375 return ret;
376 }
377 LOG_DBG("status: 0x%x", status);
378 } while (status & SPI_NOR_WIP_BIT);
379
380 if (data->dev_cfg.io_mode != MSPI_IO_MODE_SINGLE) {
381 data->timing_cfg = bkp;
382 if (mspi_timing_config(cfg->bus, &cfg->dev_id, cfg->timing_cfg_mask,
383 (void *)&data->timing_cfg)) {
384 LOG_ERR("Failed to config mspi controller/%u", __LINE__);
385 return -EIO;
386 }
387 }
388
389 return ret;
390 }
391
flash_mspi_atxp032_read(const struct device * flash,off_t offset,void * rdata,size_t len)392 static int flash_mspi_atxp032_read(const struct device *flash, off_t offset, void *rdata,
393 size_t len)
394 {
395 const struct flash_mspi_atxp032_config *cfg = flash->config;
396 struct flash_mspi_atxp032_data *data = flash->data;
397
398 int ret;
399
400 acquire(flash);
401
402 data->packet.dir = MSPI_RX;
403 data->packet.cmd = data->dev_cfg.read_cmd;
404 data->packet.address = offset;
405 data->packet.data_buf = rdata;
406 data->packet.num_bytes = len;
407
408 data->trans.async = false;
409 data->trans.xfer_mode = MSPI_DMA;
410 data->trans.rx_dummy = data->dev_cfg.rx_dummy;
411 data->trans.cmd_length = data->dev_cfg.cmd_length;
412 data->trans.addr_length = data->dev_cfg.addr_length;
413 data->trans.hold_ce = false;
414 data->trans.priority = 1;
415 data->trans.packets = &data->packet;
416 data->trans.num_packet = 1;
417 data->trans.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE;
418
419 LOG_DBG("Read %d bytes from 0x%08zx", len, (ssize_t)offset);
420
421 ret = mspi_transceive(cfg->bus, &cfg->dev_id, (const struct mspi_xfer *)&data->trans);
422 if (ret) {
423 LOG_ERR("MSPI read transaction failed with code: %d/%u", ret, __LINE__);
424 return -EIO;
425 }
426
427 release(flash);
428
429 return ret;
430 }
431
flash_mspi_atxp032_write(const struct device * flash,off_t offset,const void * wdata,size_t len)432 static int flash_mspi_atxp032_write(const struct device *flash, off_t offset, const void *wdata,
433 size_t len)
434 {
435 int ret;
436 uint8_t *src = (uint8_t *)wdata;
437 int i;
438
439 acquire(flash);
440
441 while (len) {
442 /* If the offset isn't a multiple of the NOR page size, we first need
443 * to write the remaining part that fits, otherwise the write could
444 * be wrapped around within the same page
445 */
446 i = MIN(SPI_NOR_PAGE_SIZE - (offset % SPI_NOR_PAGE_SIZE), len);
447
448 ret = flash_mspi_atxp032_write_enable(flash);
449 if (ret) {
450 return ret;
451 }
452
453 ret = flash_mspi_atxp032_page_program(flash, offset, src, i);
454 if (ret) {
455 return ret;
456 }
457
458 ret = flash_mspi_atxp032_busy_wait(flash);
459 if (ret) {
460 return ret;
461 }
462
463 src += i;
464 offset += i;
465 len -= i;
466 }
467
468 ret = flash_mspi_atxp032_write_disable(flash);
469 if (ret) {
470 return ret;
471 }
472
473 release(flash);
474
475 return ret;
476 }
477
flash_mspi_atxp032_erase(const struct device * flash,off_t offset,size_t size)478 static int flash_mspi_atxp032_erase(const struct device *flash, off_t offset, size_t size)
479 {
480 const struct flash_mspi_atxp032_config *cfg = flash->config;
481 int ret = 0;
482 const size_t num_sectors = size / SPI_NOR_SECTOR_SIZE;
483 const size_t num_blocks = size / SPI_NOR_BLOCK_SIZE;
484
485 int i;
486
487 acquire(flash);
488
489 if (offset % SPI_NOR_SECTOR_SIZE) {
490 LOG_ERR("Invalid offset");
491 return -EINVAL;
492 }
493
494 if (size % SPI_NOR_SECTOR_SIZE) {
495 LOG_ERR("Invalid size");
496 return -EINVAL;
497 }
498
499 if ((offset == 0) && (size == cfg->mem_size)) {
500 ret = flash_mspi_atxp032_write_enable(flash);
501 if (ret) {
502 return ret;
503 }
504
505 ret = flash_mspi_atxp032_erase_chip(flash);
506 if (ret) {
507 return ret;
508 }
509
510 ret = flash_mspi_atxp032_busy_wait(flash);
511 if (ret) {
512 return ret;
513 }
514
515 } else if ((0 == (offset % SPI_NOR_BLOCK_SIZE)) && (0 == (size % SPI_NOR_BLOCK_SIZE))) {
516 for (i = 0; i < num_blocks; i++) {
517 ret = flash_mspi_atxp032_write_enable(flash);
518 if (ret) {
519 return ret;
520 }
521
522 ret = flash_mspi_atxp032_unprotect_sector(flash, offset);
523 if (ret) {
524 return ret;
525 }
526
527 ret = flash_mspi_atxp032_write_enable(flash);
528 if (ret) {
529 return ret;
530 }
531
532 ret = flash_mspi_atxp032_erase_block(flash, offset);
533 if (ret) {
534 return ret;
535 }
536
537 ret = flash_mspi_atxp032_busy_wait(flash);
538 if (ret) {
539 return ret;
540 }
541
542 offset += SPI_NOR_BLOCK_SIZE;
543 }
544 } else {
545 for (i = 0; i < num_sectors; i++) {
546 ret = flash_mspi_atxp032_write_enable(flash);
547 if (ret) {
548 return ret;
549 }
550
551 ret = flash_mspi_atxp032_unprotect_sector(flash, offset);
552 if (ret) {
553 return ret;
554 }
555
556 ret = flash_mspi_atxp032_write_enable(flash);
557 if (ret) {
558 return ret;
559 }
560
561 ret = flash_mspi_atxp032_erase_sector(flash, offset);
562 if (ret) {
563 return ret;
564 }
565
566 ret = flash_mspi_atxp032_busy_wait(flash);
567 if (ret) {
568 return ret;
569 }
570
571 offset += SPI_NOR_SECTOR_SIZE;
572 }
573 }
574
575 release(flash);
576
577 return ret;
578 }
579
flash_mspi_atxp032_get_parameters(const struct device * flash)580 static const struct flash_parameters *flash_mspi_atxp032_get_parameters(const struct device *flash)
581 {
582 const struct flash_mspi_atxp032_config *cfg = flash->config;
583
584 return &cfg->flash_param;
585 }
586
587 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
flash_mspi_atxp032_pages_layout(const struct device * flash,const struct flash_pages_layout ** layout,size_t * layout_size)588 static void flash_mspi_atxp032_pages_layout(const struct device *flash,
589 const struct flash_pages_layout **layout,
590 size_t *layout_size)
591 {
592 const struct flash_mspi_atxp032_config *cfg = flash->config;
593
594 *layout = &cfg->page_layout;
595 *layout_size = 1;
596 }
597 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
598
flash_mspi_atxp032_init(const struct device * flash)599 static int flash_mspi_atxp032_init(const struct device *flash)
600 {
601 const struct flash_mspi_atxp032_config *cfg = flash->config;
602 struct flash_mspi_atxp032_data *data = flash->data;
603 uint8_t vendor_id;
604 uint32_t CRB3;
605
606 if (!device_is_ready(cfg->bus)) {
607 LOG_ERR("Controller device is not ready");
608 return -ENODEV;
609 }
610
611 switch (cfg->tar_dev_cfg.io_mode) {
612 case MSPI_IO_MODE_SINGLE:
613 case MSPI_IO_MODE_QUAD:
614 case MSPI_IO_MODE_OCTAL:
615 break;
616 default:
617 LOG_ERR("bus mode %d not supported/%u", cfg->tar_dev_cfg.io_mode, __LINE__);
618 return -EIO;
619 }
620
621 if (mspi_dev_config(cfg->bus, &cfg->dev_id, MSPI_DEVICE_CONFIG_ALL, &cfg->serial_cfg)) {
622 LOG_ERR("Failed to config mspi controller/%u", __LINE__);
623 return -EIO;
624 }
625 data->dev_cfg = cfg->serial_cfg;
626
627 if (flash_mspi_atxp032_reset(flash)) {
628 LOG_ERR("Could not reset Flash/%u", __LINE__);
629 return -EIO;
630 }
631
632 if (flash_mspi_atxp032_get_vendor_id(flash, &vendor_id)) {
633 LOG_ERR("Could not read vendor id/%u", __LINE__);
634 return -EIO;
635 }
636 LOG_DBG("Vendor id: 0x%0x", vendor_id);
637 if (vendor_id != ATXP032_VENDOR_ID) {
638 LOG_WRN("Vendor ID does not match expected value of 0x%0x/%u", ATXP032_VENDOR_ID,
639 __LINE__);
640 }
641
642 if (atxp032_get_dummy_clk((TIMING_CFG_GET_RX_DUMMY(&cfg->tar_timing_cfg)), &CRB3)) {
643 return -ENOTSUP;
644 }
645
646 if (flash_mspi_atxp032_write_enable(flash)) {
647 return -EIO;
648 }
649
650 if (flash_mspi_atxp032_command_write(flash, 0x71, 0x3, 1, 0, (uint8_t *)&CRB3, 1)) {
651 return -EIO;
652 }
653
654 uint8_t cmd;
655
656 if (cfg->tar_dev_cfg.io_mode == MSPI_IO_MODE_QUAD) {
657 cmd = 0x38;
658 } else if (cfg->tar_dev_cfg.io_mode == MSPI_IO_MODE_OCTAL) {
659 cmd = 0xe8;
660 } else {
661 cmd = 0xff;
662 }
663
664 if (flash_mspi_atxp032_write_enable(flash)) {
665 return -EIO;
666 }
667 if (flash_mspi_atxp032_command_write(flash, cmd, 0, 0, 0, NULL, 0)) {
668 return -EIO;
669 }
670
671 if (mspi_dev_config(cfg->bus, &cfg->dev_id, MSPI_DEVICE_CONFIG_ALL, &cfg->tar_dev_cfg)) {
672 LOG_ERR("Failed to config mspi controller/%u", __LINE__);
673 return -EIO;
674 }
675 data->dev_cfg = cfg->tar_dev_cfg;
676
677 if (mspi_timing_config(cfg->bus, &cfg->dev_id, cfg->timing_cfg_mask,
678 (void *)&cfg->tar_timing_cfg)) {
679 LOG_ERR("Failed to config mspi timing/%u", __LINE__);
680 return -EIO;
681 }
682 data->timing_cfg = cfg->tar_timing_cfg;
683
684 if (cfg->tar_xip_cfg.enable) {
685 if (mspi_xip_config(cfg->bus, &cfg->dev_id, &cfg->tar_xip_cfg)) {
686 LOG_ERR("Failed to enable XIP/%u", __LINE__);
687 return -EIO;
688 }
689 data->xip_cfg = cfg->tar_xip_cfg;
690 }
691
692 if (cfg->tar_scramble_cfg.enable) {
693 if (mspi_scramble_config(cfg->bus, &cfg->dev_id, &cfg->tar_scramble_cfg)) {
694 LOG_ERR("Failed to enable scrambling/%u", __LINE__);
695 return -EIO;
696 }
697 data->scramble_cfg = cfg->tar_scramble_cfg;
698 }
699
700 release(flash);
701
702 return 0;
703 }
704
705 #if defined(CONFIG_FLASH_JESD216_API)
flash_mspi_atxp032_read_sfdp(const struct device * flash,off_t addr,void * rdata,size_t size)706 static int flash_mspi_atxp032_read_sfdp(const struct device *flash, off_t addr, void *rdata,
707 size_t size)
708 {
709 const struct flash_mspi_atxp032_config *cfg = flash->config;
710 struct flash_mspi_atxp032_data *data = flash->data;
711 int ret;
712
713 acquire(flash);
714
715 data->packet.dir = MSPI_RX;
716 data->packet.cmd = 0x5A;
717 data->packet.address = addr;
718 data->packet.data_buf = rdata;
719 data->packet.num_bytes = size;
720
721 data->trans.async = false;
722 data->trans.xfer_mode = MSPI_DMA;
723 data->trans.rx_dummy = 8;
724 data->trans.cmd_length = 1;
725 data->trans.addr_length = 3;
726 data->trans.hold_ce = false;
727 data->trans.priority = 1;
728 data->trans.packets = &data->packet;
729 data->trans.num_packet = 1;
730 data->trans.timeout = CONFIG_MSPI_COMPLETION_TIMEOUT_TOLERANCE;
731
732 LOG_DBG("Read %d bytes from 0x%08zx", size, (ssize_t)addr);
733
734 ret = mspi_transceive(cfg->bus, &cfg->dev_id, (const struct mspi_xfer *)&data->trans);
735
736 if (ret) {
737 LOG_ERR("MSPI read transaction failed with code: %d/%u", ret, __LINE__);
738 return -EIO;
739 }
740
741 release(flash);
742 return 0;
743 }
flash_mspi_atxp032_read_jedec_id(const struct device * flash,uint8_t * id)744 static int flash_mspi_atxp032_read_jedec_id(const struct device *flash, uint8_t *id)
745 {
746 struct flash_mspi_atxp032_data *data = flash->data;
747
748 id = &data->jedec_id;
749 return 0;
750 }
751 #endif /* CONFIG_FLASH_JESD216_API */
752
753 #if defined(CONFIG_PM_DEVICE)
flash_mspi_atxp032_pm_action(const struct device * flash,enum pm_device_action action)754 static int flash_mspi_atxp032_pm_action(const struct device *flash, enum pm_device_action action)
755 {
756 switch (action) {
757 case PM_DEVICE_ACTION_RESUME:
758 acquire(flash);
759
760 release(flash);
761 break;
762
763 case PM_DEVICE_ACTION_SUSPEND:
764 acquire(flash);
765
766 release(flash);
767 break;
768
769 default:
770 return -ENOTSUP;
771 }
772
773 return 0;
774 }
775 #endif /** IS_ENABLED(CONFIG_PM_DEVICE) */
776
777 static DEVICE_API(flash, flash_mspi_atxp032_api) = {
778 .erase = flash_mspi_atxp032_erase,
779 .write = flash_mspi_atxp032_write,
780 .read = flash_mspi_atxp032_read,
781 .get_parameters = flash_mspi_atxp032_get_parameters,
782 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
783 .page_layout = flash_mspi_atxp032_pages_layout,
784 #endif
785 #if defined(CONFIG_FLASH_JESD216_API)
786 .sfdp_read = flash_mspi_atxp032_read_sfdp,
787 .read_jedec_id = flash_mspi_atxp032_read_jedec_id,
788 #endif
789 };
790
791 #define MSPI_DEVICE_CONFIG_SERIAL(n) \
792 { \
793 .ce_num = DT_INST_PROP(n, mspi_hardware_ce_num), \
794 .freq = 12000000, \
795 .io_mode = MSPI_IO_MODE_SINGLE, \
796 .data_rate = MSPI_DATA_RATE_SINGLE, \
797 .cpp = MSPI_CPP_MODE_0, \
798 .endian = MSPI_XFER_LITTLE_ENDIAN, \
799 .ce_polarity = MSPI_CE_ACTIVE_LOW, \
800 .dqs_enable = false, \
801 .rx_dummy = 8, \
802 .tx_dummy = 0, \
803 .read_cmd = SPI_NOR_CMD_READ_FAST, \
804 .write_cmd = SPI_NOR_CMD_PP, \
805 .cmd_length = 1, \
806 .addr_length = 4, \
807 .mem_boundary = 0, \
808 .time_to_break = 0, \
809 }
810
811 #if CONFIG_SOC_FAMILY_AMBIQ
812 #define MSPI_TIMING_CONFIG(n) \
813 { \
814 .ui8WriteLatency = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 0), \
815 .ui8TurnAround = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 1), \
816 .bTxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 2), \
817 .bRxNeg = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 3), \
818 .bRxCap = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 4), \
819 .ui32TxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 5), \
820 .ui32RxDQSDelay = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 6), \
821 .ui32RXDQSDelayEXT = DT_INST_PROP_BY_IDX(n, ambiq_timing_config, 7), \
822 }
823 #define MSPI_TIMING_CONFIG_MASK(n) DT_INST_PROP(n, ambiq_timing_config_mask)
824 #else
825 #define MSPI_TIMING_CONFIG(n)
826 #define MSPI_TIMING_CONFIG_MASK(n)
827 #endif
828
829 #define FLASH_MSPI_ATXP032(n) \
830 static const struct flash_mspi_atxp032_config flash_mspi_atxp032_config_##n = { \
831 .mem_size = DT_INST_PROP(n, size) / 8, \
832 .port = MSPI_PORT(n), \
833 .flash_param = \
834 { \
835 .write_block_size = NOR_WRITE_SIZE, \
836 .erase_value = NOR_ERASE_VALUE, \
837 }, \
838 .page_layout = \
839 { \
840 .pages_count = DT_INST_PROP(n, size) / 8 / SPI_NOR_PAGE_SIZE, \
841 .pages_size = SPI_NOR_PAGE_SIZE, \
842 }, \
843 .bus = DEVICE_DT_GET(DT_INST_BUS(n)), \
844 .dev_id = MSPI_DEVICE_ID_DT_INST(n), \
845 .serial_cfg = MSPI_DEVICE_CONFIG_SERIAL(n), \
846 .tar_dev_cfg = MSPI_DEVICE_CONFIG_DT_INST(n), \
847 .tar_xip_cfg = MSPI_XIP_CONFIG_DT_INST(n), \
848 .tar_scramble_cfg = MSPI_SCRAMBLE_CONFIG_DT_INST(n), \
849 .tar_timing_cfg = MSPI_TIMING_CONFIG(n), \
850 .timing_cfg_mask = MSPI_TIMING_CONFIG_MASK(n), \
851 .sw_multi_periph = DT_PROP(DT_INST_BUS(n), software_multiperipheral) \
852 }; \
853 static struct flash_mspi_atxp032_data flash_mspi_atxp032_data_##n = { \
854 .lock = Z_SEM_INITIALIZER(flash_mspi_atxp032_data_##n.lock, 0, 1), \
855 }; \
856 PM_DEVICE_DT_INST_DEFINE(n, flash_mspi_atxp032_pm_action); \
857 DEVICE_DT_INST_DEFINE(n, \
858 flash_mspi_atxp032_init, \
859 PM_DEVICE_DT_INST_GET(n), \
860 &flash_mspi_atxp032_data_##n, \
861 &flash_mspi_atxp032_config_##n, \
862 POST_KERNEL, \
863 CONFIG_FLASH_INIT_PRIORITY, \
864 &flash_mspi_atxp032_api);
865
866 DT_INST_FOREACH_STATUS_OKAY(FLASH_MSPI_ATXP032)
867
