1 /* 2 * Copyright (c) 2024 Robert Slawinski <robert.slawinski1@gmail.com> 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* The absolute PHY address is 10 bit length. Last 5 bits for oldest 8 * part of address - see Clause 22 of IEEE 802.3. 9 */ 10 #define DM8806_REGAD_WIDTH 0x5u 11 12 /* Mask for checksum error. Checksum status is present on the 8-th bit of the 13 * Serial Bus Error Check Register (339h) [8] 14 */ 15 #define DM8806_SMI_ERR 8 16 17 /* PHY read opcode as part of the MDIO frame in Clause 22 */ 18 #define DM8806_PHY_READ 0x2u 19 /* PHY write opcode as part of the MDIO frame in Clause 22 */ 20 #define DM8806_PHY_WRITE 0x1u 21 22 /* Port 0~4 PHY Control Register. */ 23 #define DM8806_PORTX_PHY_CONTROL_REGISTER 0x0u 24 /* 10 Mbit/s transfer with half duplex mask. */ 25 #define DM8806_MODE_10_BASET_HALF_DUPLEX 0x0u 26 /* 10 Mbit/s transfer with full duplex mask. */ 27 #define DM8806_MODE_10_BASET_FULL_DUPLEX 0x100u 28 /* 100 Mbit/s transfer with half duplex mask. */ 29 #define DM8806_MODE_100_BASET_HALF_DUPLEX 0x2000u 30 /* 100 Mbit/s transfer with full duplex mask. */ 31 #define DM8806_MODE_100_BASET_FULL_DUPLEX 0x2100u 32 /* Duplex mode ability offset. */ 33 #define DM8806_DUPLEX_MODE (1 << 8) 34 /* Power down mode offset. */ 35 #define DM8806_POWER_DOWN (1 << 11) 36 /* Auto negotiation mode offset. */ 37 #define DM8806_AUTO_NEGOTIATION (1 << 12) 38 /* Link speed selection offset. */ 39 #define DM8806_LINK_SPEED (1 << 13) 40 41 /* Port 0~4 Status Data Register. */ 42 #define DM8806_PORTX_SWITCH_STATUS 0x10u 43 /* 10 Mbit/s transfer speed with half duplex. */ 44 #define DM8806_SPEED_10MBPS_HALF_DUPLEX 0x00u 45 /* 10 Mbit/s transfer speed with full duplex. */ 46 #define DM8806_SPEED_10MBPS_FULL_DUPLEX 0x01u 47 /* 100 Mbit/s transfer speed with half duplex. */ 48 #define DM8806_SPEED_100MBPS_HALF_DUPLEX 0x02u 49 /* 100 Mbit/s transfer speed with full duplex. */ 50 #define DM8806_SPEED_100MBPS_FULL_DUPLEX 0x03u 51 /* Speed and duplex mode status offset. */ 52 #define DM8806_SPEED_AND_DUPLEX_OFFSET 0x01u 53 /* Speed and duplex mode staus mask. */ 54 #define DM8806_SPEED_AND_DUPLEX_MASK 0x07u 55 /* Link status mask. */ 56 #define DM8806_LINK_STATUS_MASK 0x1u 57 58 /* Switch Engine Registers */ 59 /* Address Table Control And Status Register PHY Address */ 60 #define DM8806_ADDR_TAB_CTRL_STAT_PHY_ADDR 0x15u 61 /* Address Table Control And Status Register Register SAddress */ 62 #define DM8806_ADDR_TAB_CTRL_STAT_REG_ADDR 0x10u 63 64 /* Address Table Access bussy flag offset */ 65 #define DM8806_ATB_S_OFFSET 0xf 66 /* Address Table Command Result flag offset */ 67 #define DM8806_ATB_CR_OFFSET 0xd 68 /* Address Table Command Result flag mask */ 69 #define DM8806_ATB_CR_MASK 0x3 70 71 /* Unicast Address Table Index*/ 72 #define DM8806_UNICAST_ADDR_TAB (1 << 0 | 1 << 1) 73 /* Multicast Address Table Index*/ 74 #define DM8806_MULTICAST_ADDR_TAB (1 << 0) 75 /* IGMP Table Index*/ 76 #define DM8806_IGMP_ADDR_TAB (1 << 1) 77 78 /* Read a entry with sequence number of address table */ 79 #define DM8806_ATB_CMD_READ (1 << 2 | 1 << 3 | 1 << 4) 80 /* Write a entry with MAC address */ 81 #define DM8806_ATB_CMD_WRITE (1 << 2) 82 /* Delete a entry with MAC address */ 83 #define DM8806_ATB_CMD_DELETE (1 << 3) 84 /* Search a entry with MAC address */ 85 #define DM8806_ATB_CMD_SEARCH (1 << 2 | 1 << 3) 86 /* Clear one or more than one entries with Port or FID */ 87 #define DM8806_ATB_CMD_CLEAR (1 << 4) 88 89 /* Address Table Data 0 PHY Address */ 90 #define DM8806_ADDR_TAB_DATA0_PHY_ADDR 0x15u 91 /* Address Table Data 0 Register Address */ 92 #define DM8806_ADDR_TAB_DATA0_REG_ADDR 0x11u 93 /* Port number or port map mask*/ 94 #define DM8806_ATB_PORT_MASK 0x1f 95 96 /* Address Table Data 1 PHY Address */ 97 #define DM8806_ADDR_TAB_DATA1_PHY_ADDR 0x15u 98 /* Address Table Data 1 Register Address */ 99 #define DM8806_ADDR_TAB_DATA1_REG_ADDR 0x12u 100 101 /* Address Table Data 2 PHY Address */ 102 #define DM8806_ADDR_TAB_DATA2_PHY_ADDR 0x15u 103 /* Address Table Data 2 Register Address */ 104 #define DM8806_ADDR_TAB_DATA2_REG_ADDR 0x13u 105 106 /* Address Table Data 3 PHY Address */ 107 #define DM8806_ADDR_TAB_DATA3_PHY_ADDR 0x15u 108 /* Address Table Data 3 Register Address */ 109 #define DM8806_ADDR_TAB_DATA3_REG_ADDR 0x14u 110 111 /* Address Table Data 4 PHY Address */ 112 #define DM8806_ADDR_TAB_DATA4_PHY_ADDR 0x15u 113 /* Address Table Data 4 Register Address */ 114 #define DM8806_ADDR_TAB_DATA4_REG_ADDR 0x15u 115 116 /* WoL Control Register PHY Address */ 117 #define DM8806_WOLL_CTRL_REG_PHY_ADDR 0x15u 118 /* WoL Control Register Register Address */ 119 #define DM8806_WOLL_CTRL_REG_REG_ADDR 0x1bu 120 121 /* Serial Bus Error Check PHY Address. */ 122 #define DM8806_SMI_BUS_ERR_CHK_PHY_ADDRESS 0x19u 123 /* Serial Bus Error Check Register Address. */ 124 #define DM8806_SMI_BUS_ERR_CHK_REG_ADDRESS 0x19u 125 126 /* Serial Bus Control PHY Address. */ 127 #define DM8806_SMI_BUS_CTRL_PHY_ADDRESS 0x19u 128 /* Serial Bus Control Register Address. */ 129 #define DM8806_SMI_BUS_CTRL_REG_ADDRESS 0x1au 130 /* SMI Bus Error Check Enable. */ 131 #define DM8806_SMI_ECE BIT(0) 132 133 /* PHY address 0x18h */ 134 #define DM8806_PHY_ADDRESS_18H 0x18u 135 136 /* Interrupt Status Register PHY Address. */ 137 #define DM8806_INT_STAT_PHY_ADDR 0x18u 138 /* Interrupt Status Register Register Address. */ 139 #define DM8806_INT_STAT_REG_ADDR 0x18u 140 141 /* Interrupt Mask & Control Register PHY Address. */ 142 #define DM8806_INT_MASK_CTRL_PHY_ADDR 0x18u 143 /* Interrupt Mask & Control Register Register Address. */ 144 #define DM8806_INT_MASK_CTRL_REG_ADDR 0x19u 145 146 /* Switch Register offset */ 147 #define DM8806_SWITCH_REGISTER_OFFSET 0x08 148 149 /* Energy Efficient Ethernet Control Register Address. */ 150 #define DM8806_ENERGY_EFFICIENT_ETH_CTRL_REG_ADDR 0x1e 151 152 /* Energy Efficient Ethernet enable bit */ 153 #define DM8806_EEE_EN BIT(15) 154 155 #define DM8806_PORT5_MAC_CONTROL 0x15u 156 /* Port 5 Force Speed control bit */ 157 #define DM8806_P5_SPEED_100M ~BIT(0) 158 /* Port 5 Force Duplex control bit */ 159 #define DM8806_P5_FULL_DUPLEX ~BIT(1) 160 /* Port 5 Force Link control bit. Only available in force mode. */ 161 #define DM8806_P5_FORCE_LINK_ON ~BIT(2) 162 /* Port 5 Force Mode Enable control bit. Only available for 163 * MII/RevMII/RMII 164 */ 165 #define DM8806_P5_EN_FORCE BIT(3) 166 /* Bit 4 is reserved and should not be use */ 167 /* Port 5 50MHz Clock Output Enable control bit. Only available when Port 5 168 * be configured as RMII 169 */ 170 #define DM8806_P5_50M_CLK_OUT_ENABLE BIT(5) 171 /* Port 5 Clock Source Selection control bit. Only available when Port 5 172 * is configured as RMII 173 */ 174 #define DM8806_P5_50M_INT_CLK_SOURCE BIT(6) 175 /* Port 5 Output Pin Slew Rate. */ 176 #define DM8806_P5_NORMAL_SLEW_RATE ~BIT(7) 177 /* IRQ and LED Control Register. */ 178 #define DM8806_IRQ_LED_CONTROL 0x17u 179 /* LED mode 0: 180 * LNK_LED: 181 * 100M link fail - LED off 182 * 100M link ok and no TX/RX activity - LED on 183 * 100M link ok and TX/RX activity - LED blinking 184 * SPD_LED: 185 * No colision: - LED off 186 * Colision: - LED blinking 187 * FDX_LED: 188 * 10M link fail - LED off 189 * 10M link ok and no TX/RX activity - LED on 190 * 10M link ok and TX/RX activity - LED blinking 191 */ 192 #define DM8806_LED_MODE_0 ~(BIT(0) | BIT(1)) 193
