1 /* W5500 Stand-alone Ethernet Controller with SPI
2 *
3 * Copyright (c) 2020 Linumiz
4 * Author: Parthiban Nallathambi <parthiban@linumiz.com>
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #define DT_DRV_COMPAT wiznet_w5500
10
11 #include <zephyr/logging/log.h>
12 LOG_MODULE_REGISTER(eth_w5500, CONFIG_ETHERNET_LOG_LEVEL);
13
14 #include <zephyr/kernel.h>
15 #include <zephyr/device.h>
16 #include <string.h>
17 #include <errno.h>
18 #include <zephyr/drivers/gpio.h>
19 #include <zephyr/drivers/spi.h>
20 #include <zephyr/net/net_pkt.h>
21 #include <zephyr/net/net_if.h>
22 #include <zephyr/net/ethernet.h>
23 #include <ethernet/eth_stats.h>
24
25 #include "eth.h"
26 #include "eth_w5500_priv.h"
27
28 #define WIZNET_OUI_B0 0x00
29 #define WIZNET_OUI_B1 0x08
30 #define WIZNET_OUI_B2 0xdc
31
32 #define W5500_SPI_BLOCK_SELECT(addr) (((addr) >> 16) & 0x1f)
33 #define W5500_SPI_READ_CONTROL(addr) (W5500_SPI_BLOCK_SELECT(addr) << 3)
34 #define W5500_SPI_WRITE_CONTROL(addr) \
35 ((W5500_SPI_BLOCK_SELECT(addr) << 3) | BIT(2))
36
w5500_spi_read(const struct device * dev,uint32_t addr,uint8_t * data,size_t len)37 static int w5500_spi_read(const struct device *dev, uint32_t addr,
38 uint8_t *data, size_t len)
39 {
40 const struct w5500_config *cfg = dev->config;
41 int ret;
42
43 uint8_t cmd[3] = {
44 addr >> 8,
45 addr,
46 W5500_SPI_READ_CONTROL(addr)
47 };
48 const struct spi_buf tx_buf = {
49 .buf = cmd,
50 .len = ARRAY_SIZE(cmd),
51 };
52 const struct spi_buf_set tx = {
53 .buffers = &tx_buf,
54 .count = 1,
55 };
56 /* skip the default dummy 0x010203 */
57 const struct spi_buf rx_buf[2] = {
58 {
59 .buf = NULL,
60 .len = 3
61 },
62 {
63 .buf = data,
64 .len = len
65 },
66 };
67 const struct spi_buf_set rx = {
68 .buffers = rx_buf,
69 .count = ARRAY_SIZE(rx_buf),
70 };
71
72 ret = spi_transceive_dt(&cfg->spi, &tx, &rx);
73
74 return ret;
75 }
76
w5500_spi_write(const struct device * dev,uint32_t addr,uint8_t * data,size_t len)77 static int w5500_spi_write(const struct device *dev, uint32_t addr,
78 uint8_t *data, size_t len)
79 {
80 const struct w5500_config *cfg = dev->config;
81 int ret;
82 uint8_t cmd[3] = {
83 addr >> 8,
84 addr,
85 W5500_SPI_WRITE_CONTROL(addr),
86 };
87 const struct spi_buf tx_buf[2] = {
88 {
89 .buf = cmd,
90 .len = ARRAY_SIZE(cmd),
91 },
92 {
93 .buf = data,
94 .len = len,
95 },
96 };
97 const struct spi_buf_set tx = {
98 .buffers = tx_buf,
99 .count = ARRAY_SIZE(tx_buf),
100 };
101
102 ret = spi_write_dt(&cfg->spi, &tx);
103
104 return ret;
105 }
106
w5500_readbuf(const struct device * dev,uint16_t offset,uint8_t * buf,size_t len)107 static int w5500_readbuf(const struct device *dev, uint16_t offset, uint8_t *buf,
108 size_t len)
109 {
110 uint32_t addr;
111 size_t remain = 0;
112 int ret;
113 const uint32_t mem_start = W5500_Sn_RX_MEM_START;
114 const uint32_t mem_size = W5500_RX_MEM_SIZE;
115
116 offset %= mem_size;
117 addr = mem_start + offset;
118
119 if (offset + len > mem_size) {
120 remain = (offset + len) % mem_size;
121 len = mem_size - offset;
122 }
123
124 ret = w5500_spi_read(dev, addr, buf, len);
125 if (ret || !remain) {
126 return ret;
127 }
128
129 return w5500_spi_read(dev, mem_start, buf + len, remain);
130 }
131
w5500_writebuf(const struct device * dev,uint16_t offset,uint8_t * buf,size_t len)132 static int w5500_writebuf(const struct device *dev, uint16_t offset, uint8_t *buf,
133 size_t len)
134 {
135 uint32_t addr;
136 size_t remain = 0;
137 int ret;
138 const uint32_t mem_start = W5500_Sn_TX_MEM_START;
139 const uint32_t mem_size = W5500_TX_MEM_SIZE;
140
141 offset %= mem_size;
142 addr = mem_start + offset;
143
144 if (offset + len > mem_size) {
145 remain = (offset + len) % mem_size;
146 len = mem_size - offset;
147 }
148
149 ret = w5500_spi_write(dev, addr, buf, len);
150 if (ret || !remain) {
151 return ret;
152 }
153
154 return w5500_spi_write(dev, mem_start, buf + len, remain);
155 }
156
w5500_command(const struct device * dev,uint8_t cmd)157 static int w5500_command(const struct device *dev, uint8_t cmd)
158 {
159 uint8_t reg;
160 k_timepoint_t end = sys_timepoint_calc(K_MSEC(100));
161
162 w5500_spi_write(dev, W5500_S0_CR, &cmd, 1);
163 while (true) {
164 w5500_spi_read(dev, W5500_S0_CR, ®, 1);
165 if (!reg) {
166 break;
167 }
168 if (sys_timepoint_expired(end)) {
169 return -EIO;
170 }
171 k_busy_wait(W5500_PHY_ACCESS_DELAY);
172 }
173 return 0;
174 }
175
w5500_tx(const struct device * dev,struct net_pkt * pkt)176 static int w5500_tx(const struct device *dev, struct net_pkt *pkt)
177 {
178 struct w5500_runtime *ctx = dev->data;
179 uint16_t len = (uint16_t)net_pkt_get_len(pkt);
180 uint16_t offset;
181 uint8_t off[2];
182 int ret;
183
184 w5500_spi_read(dev, W5500_S0_TX_WR, off, 2);
185 offset = sys_get_be16(off);
186
187 if (net_pkt_read(pkt, ctx->buf, len)) {
188 return -EIO;
189 }
190
191 ret = w5500_writebuf(dev, offset, ctx->buf, len);
192 if (ret < 0) {
193 return ret;
194 }
195
196 sys_put_be16(offset + len, off);
197 w5500_spi_write(dev, W5500_S0_TX_WR, off, 2);
198
199 w5500_command(dev, S0_CR_SEND);
200 if (k_sem_take(&ctx->tx_sem, K_MSEC(10))) {
201 return -EIO;
202 }
203
204 return 0;
205 }
206
w5500_rx(const struct device * dev)207 static void w5500_rx(const struct device *dev)
208 {
209 uint8_t header[2];
210 uint8_t tmp[2];
211 uint16_t off;
212 uint16_t rx_len;
213 uint16_t rx_buf_len;
214 uint16_t read_len;
215 uint16_t reader;
216 struct net_buf *pkt_buf = NULL;
217 struct net_pkt *pkt;
218 struct w5500_runtime *ctx = dev->data;
219 const struct w5500_config *config = dev->config;
220
221 w5500_spi_read(dev, W5500_S0_RX_RSR, tmp, 2);
222 rx_buf_len = sys_get_be16(tmp);
223
224 if (rx_buf_len == 0) {
225 return;
226 }
227
228 w5500_spi_read(dev, W5500_S0_RX_RD, tmp, 2);
229 off = sys_get_be16(tmp);
230
231 w5500_readbuf(dev, off, header, 2);
232 rx_len = sys_get_be16(header) - 2;
233
234 pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, rx_len,
235 AF_UNSPEC, 0, K_MSEC(config->timeout));
236 if (!pkt) {
237 eth_stats_update_errors_rx(ctx->iface);
238 return;
239 }
240
241 pkt_buf = pkt->buffer;
242
243 read_len = rx_len;
244 reader = off + 2;
245
246 do {
247 size_t frag_len;
248 uint8_t *data_ptr;
249 size_t frame_len;
250
251 data_ptr = pkt_buf->data;
252
253 frag_len = net_buf_tailroom(pkt_buf);
254
255 if (read_len > frag_len) {
256 frame_len = frag_len;
257 } else {
258 frame_len = read_len;
259 }
260
261 w5500_readbuf(dev, reader, data_ptr, frame_len);
262 net_buf_add(pkt_buf, frame_len);
263 reader += (uint16_t)frame_len;
264
265 read_len -= (uint16_t)frame_len;
266 pkt_buf = pkt_buf->frags;
267 } while (read_len > 0);
268
269 if (net_recv_data(ctx->iface, pkt) < 0) {
270 net_pkt_unref(pkt);
271 }
272
273 sys_put_be16(off + 2 + rx_len, tmp);
274 w5500_spi_write(dev, W5500_S0_RX_RD, tmp, 2);
275 w5500_command(dev, S0_CR_RECV);
276 }
277
w5500_update_link_status(const struct device * dev)278 static void w5500_update_link_status(const struct device *dev)
279 {
280 uint8_t phycfgr;
281 struct w5500_runtime *ctx = dev->data;
282
283 if (w5500_spi_read(dev, W5500_PHYCFGR, &phycfgr, 1) < 0) {
284 return;
285 }
286
287 if (phycfgr & 0x01) {
288 if (ctx->link_up != true) {
289 LOG_INF("%s: Link up", dev->name);
290 ctx->link_up = true;
291 net_eth_carrier_on(ctx->iface);
292 }
293 } else {
294 if (ctx->link_up != false) {
295 LOG_INF("%s: Link down", dev->name);
296 ctx->link_up = false;
297 net_eth_carrier_off(ctx->iface);
298 }
299 }
300 }
301
w5500_thread(void * p1,void * p2,void * p3)302 static void w5500_thread(void *p1, void *p2, void *p3)
303 {
304 ARG_UNUSED(p2);
305 ARG_UNUSED(p3);
306
307 const struct device *dev = p1;
308 uint8_t ir;
309 int res;
310 struct w5500_runtime *ctx = dev->data;
311 const struct w5500_config *config = dev->config;
312
313 while (true) {
314 res = k_sem_take(&ctx->int_sem, K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
315
316 if (res == 0) {
317 /* semaphore taken, update link status and receive packets */
318 if (ctx->link_up != true) {
319 w5500_update_link_status(dev);
320 }
321
322 while (gpio_pin_get_dt(&(config->interrupt))) {
323 /* Read interrupt */
324 w5500_spi_read(dev, W5500_S0_IR, &ir, 1);
325
326 if (ir) {
327 /* Clear interrupt */
328 w5500_spi_write(dev, W5500_S0_IR, &ir, 1);
329
330 LOG_DBG("IR received");
331
332 if (ir & S0_IR_SENDOK) {
333 k_sem_give(&ctx->tx_sem);
334 LOG_DBG("TX Done");
335 }
336
337 if (ir & S0_IR_RECV) {
338 w5500_rx(dev);
339 LOG_DBG("RX Done");
340 }
341 }
342 }
343 } else if (res == -EAGAIN) {
344 /* semaphore timeout period expired, check link status */
345 w5500_update_link_status(dev);
346 }
347 }
348 }
349
w5500_iface_init(struct net_if * iface)350 static void w5500_iface_init(struct net_if *iface)
351 {
352 const struct device *dev = net_if_get_device(iface);
353 struct w5500_runtime *ctx = dev->data;
354
355 net_if_set_link_addr(iface, ctx->mac_addr,
356 sizeof(ctx->mac_addr),
357 NET_LINK_ETHERNET);
358
359 if (!ctx->iface) {
360 ctx->iface = iface;
361 }
362
363 ethernet_init(iface);
364
365 /* Do not start the interface until PHY link is up */
366 net_if_carrier_off(iface);
367 }
368
w5500_get_capabilities(const struct device * dev)369 static enum ethernet_hw_caps w5500_get_capabilities(const struct device *dev)
370 {
371 ARG_UNUSED(dev);
372
373 return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T
374 #if defined(CONFIG_NET_PROMISCUOUS_MODE)
375 | ETHERNET_PROMISC_MODE
376 #endif
377 ;
378 }
379
w5500_set_config(const struct device * dev,enum ethernet_config_type type,const struct ethernet_config * config)380 static int w5500_set_config(const struct device *dev,
381 enum ethernet_config_type type,
382 const struct ethernet_config *config)
383 {
384 struct w5500_runtime *ctx = dev->data;
385
386 switch (type) {
387 case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
388 memcpy(ctx->mac_addr,
389 config->mac_address.addr,
390 sizeof(ctx->mac_addr));
391 w5500_spi_write(dev, W5500_SHAR, ctx->mac_addr, sizeof(ctx->mac_addr));
392 LOG_INF("%s MAC set to %02x:%02x:%02x:%02x:%02x:%02x",
393 dev->name,
394 ctx->mac_addr[0], ctx->mac_addr[1],
395 ctx->mac_addr[2], ctx->mac_addr[3],
396 ctx->mac_addr[4], ctx->mac_addr[5]);
397
398 /* Register Ethernet MAC Address with the upper layer */
399 net_if_set_link_addr(ctx->iface, ctx->mac_addr,
400 sizeof(ctx->mac_addr),
401 NET_LINK_ETHERNET);
402
403 return 0;
404 case ETHERNET_CONFIG_TYPE_PROMISC_MODE:
405 if (IS_ENABLED(CONFIG_NET_PROMISCUOUS_MODE)) {
406 uint8_t mode;
407 uint8_t mr = W5500_S0_MR_MF;
408
409 w5500_spi_read(dev, W5500_S0_MR, &mode, 1);
410
411 if (config->promisc_mode) {
412 if (!(mode & BIT(mr))) {
413 return -EALREADY;
414 }
415
416 /* disable MAC filtering */
417 WRITE_BIT(mode, mr, 0);
418 } else {
419 if (mode & BIT(mr)) {
420 return -EALREADY;
421 }
422
423 /* enable MAC filtering */
424 WRITE_BIT(mode, mr, 1);
425 }
426
427 return w5500_spi_write(dev, W5500_S0_MR, &mode, 1);
428 }
429
430 return -ENOTSUP;
431 default:
432 return -ENOTSUP;
433 }
434 }
435
w5500_hw_start(const struct device * dev)436 static int w5500_hw_start(const struct device *dev)
437 {
438 uint8_t mode = S0_MR_MACRAW | BIT(W5500_S0_MR_MF);
439 uint8_t mask = IR_S0;
440
441 /* configure Socket 0 with MACRAW mode and MAC filtering enabled */
442 w5500_spi_write(dev, W5500_S0_MR, &mode, 1);
443 w5500_command(dev, S0_CR_OPEN);
444
445 /* enable interrupt */
446 w5500_spi_write(dev, W5500_SIMR, &mask, 1);
447
448 return 0;
449 }
450
w5500_hw_stop(const struct device * dev)451 static int w5500_hw_stop(const struct device *dev)
452 {
453 uint8_t mask = 0;
454
455 /* disable interrupt */
456 w5500_spi_write(dev, W5500_SIMR, &mask, 1);
457 w5500_command(dev, S0_CR_CLOSE);
458
459 return 0;
460 }
461
462 static const struct ethernet_api w5500_api_funcs = {
463 .iface_api.init = w5500_iface_init,
464 .get_capabilities = w5500_get_capabilities,
465 .set_config = w5500_set_config,
466 .start = w5500_hw_start,
467 .stop = w5500_hw_stop,
468 .send = w5500_tx,
469 };
470
w5500_soft_reset(const struct device * dev)471 static int w5500_soft_reset(const struct device *dev)
472 {
473 int ret;
474 uint8_t mask = 0;
475 uint8_t tmp = MR_RST;
476
477 ret = w5500_spi_write(dev, W5500_MR, &tmp, 1);
478 if (ret < 0) {
479 return ret;
480 }
481
482 k_msleep(5);
483 tmp = MR_PB;
484 w5500_spi_write(dev, W5500_MR, &tmp, 1);
485
486 /* disable interrupt */
487 return w5500_spi_write(dev, W5500_SIMR, &mask, 1);
488 }
489
w5500_gpio_callback(const struct device * dev,struct gpio_callback * cb,uint32_t pins)490 static void w5500_gpio_callback(const struct device *dev,
491 struct gpio_callback *cb,
492 uint32_t pins)
493 {
494 struct w5500_runtime *ctx =
495 CONTAINER_OF(cb, struct w5500_runtime, gpio_cb);
496
497 k_sem_give(&ctx->int_sem);
498 }
499
w5500_set_macaddr(const struct device * dev)500 static void w5500_set_macaddr(const struct device *dev)
501 {
502 struct w5500_runtime *ctx = dev->data;
503
504 #if DT_INST_PROP(0, zephyr_random_mac_address)
505 gen_random_mac(ctx->mac_addr, WIZNET_OUI_B0, WIZNET_OUI_B1, WIZNET_OUI_B2);
506 #endif
507
508 w5500_spi_write(dev, W5500_SHAR, ctx->mac_addr, sizeof(ctx->mac_addr));
509 }
510
w5500_memory_configure(const struct device * dev)511 static void w5500_memory_configure(const struct device *dev)
512 {
513 int i;
514 uint8_t mem = 0x10;
515
516 /* Configure RX & TX memory to 16K */
517 w5500_spi_write(dev, W5500_Sn_RXMEM_SIZE(0), &mem, 1);
518 w5500_spi_write(dev, W5500_Sn_TXMEM_SIZE(0), &mem, 1);
519
520 mem = 0;
521 for (i = 1; i < 8; i++) {
522 w5500_spi_write(dev, W5500_Sn_RXMEM_SIZE(i), &mem, 1);
523 w5500_spi_write(dev, W5500_Sn_TXMEM_SIZE(i), &mem, 1);
524 }
525 }
526
w5500_init(const struct device * dev)527 static int w5500_init(const struct device *dev)
528 {
529 int err;
530 uint8_t rtr[2];
531 const struct w5500_config *config = dev->config;
532 struct w5500_runtime *ctx = dev->data;
533
534 ctx->link_up = false;
535
536 if (!spi_is_ready_dt(&config->spi)) {
537 LOG_ERR("SPI master port %s not ready", config->spi.bus->name);
538 return -EINVAL;
539 }
540
541 if (!gpio_is_ready_dt(&config->interrupt)) {
542 LOG_ERR("GPIO port %s not ready", config->interrupt.port->name);
543 return -EINVAL;
544 }
545
546 if (gpio_pin_configure_dt(&config->interrupt, GPIO_INPUT)) {
547 LOG_ERR("Unable to configure GPIO pin %u", config->interrupt.pin);
548 return -EINVAL;
549 }
550
551 gpio_init_callback(&(ctx->gpio_cb), w5500_gpio_callback,
552 BIT(config->interrupt.pin));
553
554 if (gpio_add_callback(config->interrupt.port, &(ctx->gpio_cb))) {
555 return -EINVAL;
556 }
557
558 gpio_pin_interrupt_configure_dt(&config->interrupt,
559 GPIO_INT_EDGE_FALLING);
560
561 if (config->reset.port) {
562 if (!gpio_is_ready_dt(&config->reset)) {
563 LOG_ERR("GPIO port %s not ready", config->reset.port->name);
564 return -EINVAL;
565 }
566 if (gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT)) {
567 LOG_ERR("Unable to configure GPIO pin %u", config->reset.pin);
568 return -EINVAL;
569 }
570 gpio_pin_set_dt(&config->reset, 0);
571 k_usleep(500);
572 }
573
574 err = w5500_soft_reset(dev);
575 if (err) {
576 LOG_ERR("Reset failed");
577 return err;
578 }
579
580 w5500_set_macaddr(dev);
581 w5500_memory_configure(dev);
582
583 /* check retry time value */
584 w5500_spi_read(dev, W5500_RTR, rtr, 2);
585 if (sys_get_be16(rtr) != RTR_DEFAULT) {
586 LOG_ERR("Unable to read RTR register");
587 return -ENODEV;
588 }
589
590 k_thread_create(&ctx->thread, ctx->thread_stack,
591 CONFIG_ETH_W5500_RX_THREAD_STACK_SIZE,
592 w5500_thread,
593 (void *)dev, NULL, NULL,
594 K_PRIO_COOP(CONFIG_ETH_W5500_RX_THREAD_PRIO),
595 0, K_NO_WAIT);
596 k_thread_name_set(&ctx->thread, "eth_w5500");
597
598 LOG_INF("W5500 Initialized");
599
600 return 0;
601 }
602
603 static struct w5500_runtime w5500_0_runtime = {
604 #if NODE_HAS_VALID_MAC_ADDR(DT_DRV_INST(0))
605 .mac_addr = DT_INST_PROP(0, local_mac_address),
606 #endif
607 .tx_sem = Z_SEM_INITIALIZER(w5500_0_runtime.tx_sem,
608 1, UINT_MAX),
609 .int_sem = Z_SEM_INITIALIZER(w5500_0_runtime.int_sem,
610 0, UINT_MAX),
611 };
612
613 static const struct w5500_config w5500_0_config = {
614 .spi = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), 0),
615 .interrupt = GPIO_DT_SPEC_INST_GET(0, int_gpios),
616 .reset = GPIO_DT_SPEC_INST_GET_OR(0, reset_gpios, { 0 }),
617 .timeout = CONFIG_ETH_W5500_TIMEOUT,
618 };
619
620 ETH_NET_DEVICE_DT_INST_DEFINE(0,
621 w5500_init, NULL,
622 &w5500_0_runtime, &w5500_0_config,
623 CONFIG_ETH_INIT_PRIORITY, &w5500_api_funcs, NET_ETH_MTU);
624
