1 /* ENC28J60 Stand-alone Ethernet Controller with SPI
2 *
3 * Copyright (c) 2016 Intel Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT microchip_enc28j60
9
10 #define LOG_MODULE_NAME eth_enc28j60
11 #define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
12
13 #include <zephyr/logging/log.h>
14 LOG_MODULE_REGISTER(LOG_MODULE_NAME);
15
16 #include <zephyr/kernel.h>
17 #include <zephyr/device.h>
18 #include <string.h>
19 #include <errno.h>
20 #include <zephyr/drivers/gpio.h>
21 #include <zephyr/drivers/spi.h>
22 #include <zephyr/net/net_pkt.h>
23 #include <zephyr/net/net_if.h>
24 #include <zephyr/net/ethernet.h>
25 #include <ethernet/eth_stats.h>
26
27 #include "eth_enc28j60_priv.h"
28 #include "eth.h"
29
30 #define D10D24S 11
31
eth_enc28j60_soft_reset(const struct device * dev)32 static int eth_enc28j60_soft_reset(const struct device *dev)
33 {
34 const struct eth_enc28j60_config *config = dev->config;
35 uint8_t buf[2] = { ENC28J60_SPI_SC, 0xFF };
36 const struct spi_buf tx_buf = {
37 .buf = buf,
38 .len = 1,
39 };
40 const struct spi_buf_set tx = {
41 .buffers = &tx_buf,
42 .count = 1
43 };
44
45 return spi_write_dt(&config->spi, &tx);
46 }
47
eth_enc28j60_set_bank(const struct device * dev,uint16_t reg_addr)48 static void eth_enc28j60_set_bank(const struct device *dev, uint16_t reg_addr)
49 {
50 const struct eth_enc28j60_config *config = dev->config;
51 uint8_t buf[2];
52 const struct spi_buf tx_buf = {
53 .buf = buf,
54 .len = 2
55 };
56 const struct spi_buf rx_buf = {
57 .buf = buf,
58 .len = 2
59 };
60 const struct spi_buf_set tx = {
61 .buffers = &tx_buf,
62 .count = 1
63 };
64 const struct spi_buf_set rx = {
65 .buffers = &rx_buf,
66 .count = 1
67 };
68
69 buf[0] = ENC28J60_SPI_RCR | ENC28J60_REG_ECON1;
70 buf[1] = 0x0;
71
72 if (!spi_transceive_dt(&config->spi, &tx, &rx)) {
73 buf[0] = ENC28J60_SPI_WCR | ENC28J60_REG_ECON1;
74 buf[1] = (buf[1] & 0xFC) | ((reg_addr >> 8) & 0x03);
75
76 spi_write_dt(&config->spi, &tx);
77 } else {
78 LOG_DBG("%s: Failure while setting bank to 0x%04x", dev->name, reg_addr);
79 }
80 }
81
eth_enc28j60_write_reg(const struct device * dev,uint16_t reg_addr,uint8_t value)82 static void eth_enc28j60_write_reg(const struct device *dev,
83 uint16_t reg_addr,
84 uint8_t value)
85 {
86 const struct eth_enc28j60_config *config = dev->config;
87 uint8_t buf[2];
88 const struct spi_buf tx_buf = {
89 .buf = buf,
90 .len = 2
91 };
92 const struct spi_buf_set tx = {
93 .buffers = &tx_buf,
94 .count = 1
95 };
96
97 buf[0] = ENC28J60_SPI_WCR | (reg_addr & 0xFF);
98 buf[1] = value;
99
100 spi_write_dt(&config->spi, &tx);
101 }
102
eth_enc28j60_read_reg(const struct device * dev,uint16_t reg_addr,uint8_t * value)103 static void eth_enc28j60_read_reg(const struct device *dev, uint16_t reg_addr,
104 uint8_t *value)
105 {
106 const struct eth_enc28j60_config *config = dev->config;
107 uint8_t buf[3];
108 const struct spi_buf tx_buf = {
109 .buf = buf,
110 .len = 2
111 };
112 const struct spi_buf_set tx = {
113 .buffers = &tx_buf,
114 .count = 1
115 };
116 struct spi_buf rx_buf = {
117 .buf = buf,
118 };
119 const struct spi_buf_set rx = {
120 .buffers = &rx_buf,
121 .count = 1
122 };
123 uint8_t rx_size = 2U;
124
125 if (reg_addr & 0xF000) {
126 rx_size = 3U;
127 }
128
129 rx_buf.len = rx_size;
130
131 buf[0] = ENC28J60_SPI_RCR | (reg_addr & 0xFF);
132 buf[1] = 0x0;
133
134 if (!spi_transceive_dt(&config->spi, &tx, &rx)) {
135 *value = buf[rx_size - 1];
136 } else {
137 LOG_DBG("%s: Failure while reading register 0x%04x", dev->name, reg_addr);
138 *value = 0U;
139 }
140 }
141
eth_enc28j60_set_eth_reg(const struct device * dev,uint16_t reg_addr,uint8_t value)142 static void eth_enc28j60_set_eth_reg(const struct device *dev,
143 uint16_t reg_addr,
144 uint8_t value)
145 {
146 const struct eth_enc28j60_config *config = dev->config;
147 uint8_t buf[2];
148 const struct spi_buf tx_buf = {
149 .buf = buf,
150 .len = 2
151 };
152 const struct spi_buf_set tx = {
153 .buffers = &tx_buf,
154 .count = 1
155 };
156
157 buf[0] = ENC28J60_SPI_BFS | (reg_addr & 0xFF);
158 buf[1] = value;
159
160 spi_write_dt(&config->spi, &tx);
161 }
162
163
eth_enc28j60_clear_eth_reg(const struct device * dev,uint16_t reg_addr,uint8_t value)164 static void eth_enc28j60_clear_eth_reg(const struct device *dev,
165 uint16_t reg_addr,
166 uint8_t value)
167 {
168 const struct eth_enc28j60_config *config = dev->config;
169 uint8_t buf[2];
170 const struct spi_buf tx_buf = {
171 .buf = buf,
172 .len = 2
173 };
174 const struct spi_buf_set tx = {
175 .buffers = &tx_buf,
176 .count = 1
177 };
178
179 buf[0] = ENC28J60_SPI_BFC | (reg_addr & 0xFF);
180 buf[1] = value;
181
182 spi_write_dt(&config->spi, &tx);
183 }
184
eth_enc28j60_write_mem(const struct device * dev,uint8_t * data_buffer,uint16_t buf_len)185 static void eth_enc28j60_write_mem(const struct device *dev,
186 uint8_t *data_buffer,
187 uint16_t buf_len)
188 {
189 const struct eth_enc28j60_config *config = dev->config;
190 uint8_t buf[1] = { ENC28J60_SPI_WBM };
191 struct spi_buf tx_buf[2] = {
192 {
193 .buf = buf,
194 .len = 1
195 },
196 };
197 const struct spi_buf_set tx = {
198 .buffers = tx_buf,
199 .count = 2
200 };
201 uint16_t num_segments;
202 uint16_t num_remaining;
203 int i;
204
205 num_segments = buf_len / MAX_BUFFER_LENGTH;
206 num_remaining = buf_len - MAX_BUFFER_LENGTH * num_segments;
207
208 for (i = 0; i < num_segments; i++, data_buffer += MAX_BUFFER_LENGTH) {
209 tx_buf[1].buf = data_buffer;
210 tx_buf[1].len = MAX_BUFFER_LENGTH;
211
212 if (spi_write_dt(&config->spi, &tx)) {
213 LOG_ERR("%s: Failed to write memory", dev->name);
214 return;
215 }
216 }
217
218 if (num_remaining > 0) {
219 tx_buf[1].buf = data_buffer;
220 tx_buf[1].len = num_remaining;
221
222 if (spi_write_dt(&config->spi, &tx)) {
223 LOG_ERR("%s: Failed to write memory", dev->name);
224 }
225 }
226 }
227
eth_enc28j60_read_mem(const struct device * dev,uint8_t * data_buffer,uint16_t buf_len)228 static void eth_enc28j60_read_mem(const struct device *dev,
229 uint8_t *data_buffer,
230 uint16_t buf_len)
231 {
232 const struct eth_enc28j60_config *config = dev->config;
233 uint8_t buf[1] = { ENC28J60_SPI_RBM };
234 const struct spi_buf tx_buf = {
235 .buf = buf,
236 .len = 1
237 };
238 const struct spi_buf_set tx = {
239 .buffers = &tx_buf,
240 .count = 1
241 };
242 struct spi_buf rx_buf[2] = {
243 {
244 .buf = NULL,
245 .len = 1
246 },
247 };
248 const struct spi_buf_set rx = {
249 .buffers = rx_buf,
250 .count = 2
251 };
252 uint16_t num_segments;
253 uint16_t num_remaining;
254 int i;
255
256 num_segments = buf_len / MAX_BUFFER_LENGTH;
257 num_remaining = buf_len - MAX_BUFFER_LENGTH * num_segments;
258
259 for (i = 0; i < num_segments; i++, data_buffer += MAX_BUFFER_LENGTH) {
260
261 rx_buf[1].buf = data_buffer;
262 rx_buf[1].len = MAX_BUFFER_LENGTH;
263
264 if (spi_transceive_dt(&config->spi, &tx, &rx)) {
265 LOG_ERR("%s: Failed to read memory", dev->name);
266 return;
267 }
268 }
269
270 if (num_remaining > 0) {
271 rx_buf[1].buf = data_buffer;
272 rx_buf[1].len = num_remaining;
273
274 if (spi_transceive_dt(&config->spi, &tx, &rx)) {
275 LOG_ERR("%s: Failed to read memory", dev->name);
276 }
277 }
278 }
279
eth_enc28j60_write_phy(const struct device * dev,uint16_t reg_addr,int16_t data)280 static void eth_enc28j60_write_phy(const struct device *dev,
281 uint16_t reg_addr,
282 int16_t data)
283 {
284 uint8_t data_mistat;
285
286 eth_enc28j60_set_bank(dev, ENC28J60_REG_MIREGADR);
287 eth_enc28j60_write_reg(dev, ENC28J60_REG_MIREGADR, reg_addr);
288 eth_enc28j60_write_reg(dev, ENC28J60_REG_MIWRL, data & 0xFF);
289 eth_enc28j60_write_reg(dev, ENC28J60_REG_MIWRH, data >> 8);
290 eth_enc28j60_set_bank(dev, ENC28J60_REG_MISTAT);
291
292 do {
293 /* wait 10.24 useconds */
294 k_busy_wait(D10D24S);
295 eth_enc28j60_read_reg(dev, ENC28J60_REG_MISTAT,
296 &data_mistat);
297 } while ((data_mistat & ENC28J60_BIT_MISTAT_BUSY));
298 }
299
eth_enc28j60_read_phy(const struct device * dev,uint16_t reg_addr,int16_t * data)300 static void eth_enc28j60_read_phy(const struct device *dev,
301 uint16_t reg_addr,
302 int16_t *data)
303 {
304 uint8_t data_mistat;
305 uint8_t lsb;
306 uint8_t msb;
307
308 eth_enc28j60_set_bank(dev, ENC28J60_REG_MIREGADR);
309 eth_enc28j60_write_reg(dev, ENC28J60_REG_MIREGADR, reg_addr);
310 eth_enc28j60_write_reg(dev, ENC28J60_REG_MICMD,
311 ENC28J60_BIT_MICMD_MIIRD);
312 eth_enc28j60_set_bank(dev, ENC28J60_REG_MISTAT);
313
314 do {
315 /* wait 10.24 useconds */
316 k_busy_wait(D10D24S);
317 eth_enc28j60_read_reg(dev, ENC28J60_REG_MISTAT,
318 &data_mistat);
319 } while ((data_mistat & ENC28J60_BIT_MISTAT_BUSY));
320
321 eth_enc28j60_set_bank(dev, ENC28J60_REG_MIREGADR);
322 eth_enc28j60_write_reg(dev, ENC28J60_REG_MICMD, 0x0);
323 eth_enc28j60_read_reg(dev, ENC28J60_REG_MIRDL, &lsb);
324 eth_enc28j60_read_reg(dev, ENC28J60_REG_MIRDH, &msb);
325
326 *data = (msb << 8) | lsb;
327 }
328
eth_enc28j60_gpio_callback(const struct device * dev,struct gpio_callback * cb,uint32_t pins)329 static void eth_enc28j60_gpio_callback(const struct device *dev,
330 struct gpio_callback *cb,
331 uint32_t pins)
332 {
333 struct eth_enc28j60_runtime *context =
334 CONTAINER_OF(cb, struct eth_enc28j60_runtime, gpio_cb);
335
336 k_sem_give(&context->int_sem);
337 }
338
eth_enc28j60_init_buffers(const struct device * dev)339 static int eth_enc28j60_init_buffers(const struct device *dev)
340 {
341 uint8_t data_estat;
342 const struct eth_enc28j60_config *config = dev->config;
343
344 /* Reception buffers initialization */
345 eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXSTL);
346 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXSTL,
347 ENC28J60_RXSTART & 0xFF);
348 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXSTH,
349 ENC28J60_RXSTART >> 8);
350 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXRDPTL,
351 ENC28J60_RXSTART & 0xFF);
352 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXRDPTH,
353 ENC28J60_RXSTART >> 8);
354 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXNDL,
355 ENC28J60_RXEND & 0xFF);
356 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXNDH,
357 ENC28J60_RXEND >> 8);
358 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXSTL,
359 ENC28J60_TXSTART & 0xFF);
360 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXSTH,
361 ENC28J60_TXSTART >> 8);
362 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXNDL,
363 ENC28J60_TXEND & 0xFF);
364 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXNDH,
365 ENC28J60_TXEND >> 8);
366 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERDPTL,
367 ENC28J60_RXSTART & 0xFF);
368 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERDPTH,
369 ENC28J60_RXSTART >> 8);
370 eth_enc28j60_write_reg(dev, ENC28J60_REG_EWRPTL,
371 ENC28J60_TXSTART & 0xFF);
372 eth_enc28j60_write_reg(dev, ENC28J60_REG_EWRPTH,
373 ENC28J60_TXSTART >> 8);
374
375 eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXFCON);
376 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXFCON,
377 config->hw_rx_filter);
378
379 /* Waiting for OST */
380 /* 32 bits for this timer should be fine, rollover not an issue with initialisation */
381 uint32_t start_wait = (uint32_t) k_uptime_get();
382 do {
383 /* If the CLK isn't ready don't wait forever */
384 if ((k_uptime_get_32() - start_wait) > CONFIG_ETH_ENC28J60_CLKRDY_INIT_WAIT_MS) {
385 LOG_ERR("OST wait timed out");
386 return -ETIMEDOUT;
387 }
388 /* wait 10.24 useconds */
389 k_busy_wait(D10D24S);
390 eth_enc28j60_read_reg(dev, ENC28J60_REG_ESTAT, &data_estat);
391 } while (!(data_estat & ENC28J60_BIT_ESTAT_CLKRDY));
392
393 return 0;
394 }
395
eth_enc28j60_init_mac(const struct device * dev)396 static void eth_enc28j60_init_mac(const struct device *dev)
397 {
398 const struct eth_enc28j60_config *config = dev->config;
399 struct eth_enc28j60_runtime *context = dev->data;
400 uint8_t data_macon;
401
402 eth_enc28j60_set_bank(dev, ENC28J60_REG_MACON1);
403
404 /* Set MARXEN to enable MAC to receive frames */
405 eth_enc28j60_read_reg(dev, ENC28J60_REG_MACON1, &data_macon);
406 data_macon |= ENC28J60_BIT_MACON1_MARXEN | ENC28J60_BIT_MACON1_RXPAUS
407 | ENC28J60_BIT_MACON1_TXPAUS;
408 eth_enc28j60_write_reg(dev, ENC28J60_REG_MACON1, data_macon);
409
410 data_macon = ENC28J60_MAC_CONFIG;
411
412 if (config->full_duplex) {
413 data_macon |= ENC28J60_BIT_MACON3_FULDPX;
414 }
415
416 eth_enc28j60_write_reg(dev, ENC28J60_REG_MACON3, data_macon);
417 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAIPGL, ENC28J60_MAC_NBBIPGL);
418
419 if (config->full_duplex) {
420 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAIPGH,
421 ENC28J60_MAC_NBBIPGH);
422 eth_enc28j60_write_reg(dev, ENC28J60_REG_MABBIPG,
423 ENC28J60_MAC_BBIPG_FD);
424 } else {
425 eth_enc28j60_write_reg(dev, ENC28J60_REG_MABBIPG,
426 ENC28J60_MAC_BBIPG_HD);
427 eth_enc28j60_write_reg(dev, ENC28J60_REG_MACON4, 1 << 6);
428 }
429
430 /* Configure MAC address */
431 eth_enc28j60_set_bank(dev, ENC28J60_REG_MAADR1);
432 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR6,
433 context->mac_address[5]);
434 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR5,
435 context->mac_address[4]);
436 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR4,
437 context->mac_address[3]);
438 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR3,
439 context->mac_address[2]);
440 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR2,
441 context->mac_address[1]);
442 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR1,
443 context->mac_address[0]);
444 }
445
eth_enc28j60_init_phy(const struct device * dev)446 static void eth_enc28j60_init_phy(const struct device *dev)
447 {
448 const struct eth_enc28j60_config *config = dev->config;
449
450 if (config->full_duplex) {
451 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHCON1,
452 ENC28J60_BIT_PHCON1_PDPXMD);
453 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHCON2, 0x0);
454 } else {
455 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHCON1, 0x0);
456 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHCON2,
457 ENC28J60_BIT_PHCON2_HDLDIS);
458 }
459 }
460
get_iface(struct eth_enc28j60_runtime * ctx)461 static struct net_if *get_iface(struct eth_enc28j60_runtime *ctx)
462 {
463 return ctx->iface;
464 }
465
eth_enc28j60_tx(const struct device * dev,struct net_pkt * pkt)466 static int eth_enc28j60_tx(const struct device *dev, struct net_pkt *pkt)
467 {
468 struct eth_enc28j60_runtime *context = dev->data;
469 uint16_t tx_bufaddr = ENC28J60_TXSTART;
470 uint16_t len = net_pkt_get_len(pkt);
471 uint8_t per_packet_control;
472 uint16_t tx_bufaddr_end;
473 struct net_buf *frag;
474 uint8_t tx_end;
475
476 LOG_DBG("%s: pkt %p (len %u)", dev->name, pkt, len);
477
478 k_sem_take(&context->tx_rx_sem, K_FOREVER);
479
480 /* Latest errata sheet: DS80349C
481 * always reset transmit logic (Errata Issue 12)
482 * the Microchip TCP/IP stack implementation used to first check
483 * whether TXERIF is set and only then reset the transmit logic
484 * but this has been changed in later versions; possibly they
485 * have a reason for this; they don't mention this in the errata
486 * sheet
487 */
488 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_ECON1,
489 ENC28J60_BIT_ECON1_TXRST);
490 eth_enc28j60_clear_eth_reg(dev, ENC28J60_REG_ECON1,
491 ENC28J60_BIT_ECON1_TXRST);
492
493 /* Write the buffer content into the transmission buffer */
494 eth_enc28j60_set_bank(dev, ENC28J60_REG_ETXSTL);
495 eth_enc28j60_write_reg(dev, ENC28J60_REG_EWRPTL, tx_bufaddr & 0xFF);
496 eth_enc28j60_write_reg(dev, ENC28J60_REG_EWRPTH, tx_bufaddr >> 8);
497 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXSTL, tx_bufaddr & 0xFF);
498 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXSTH, tx_bufaddr >> 8);
499
500 /* Write the data into the buffer */
501 per_packet_control = ENC28J60_PPCTL_BYTE;
502 eth_enc28j60_write_mem(dev, &per_packet_control, 1);
503
504 for (frag = pkt->frags; frag; frag = frag->frags) {
505 eth_enc28j60_write_mem(dev, frag->data, frag->len);
506 }
507
508 tx_bufaddr_end = tx_bufaddr + len;
509 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXNDL,
510 tx_bufaddr_end & 0xFF);
511 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXNDH, tx_bufaddr_end >> 8);
512
513 /* Signal ENC28J60 to send the buffer */
514 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_ECON1,
515 ENC28J60_BIT_ECON1_TXRTS);
516
517 do {
518 /* wait 10.24 useconds */
519 k_busy_wait(D10D24S);
520 eth_enc28j60_read_reg(dev, ENC28J60_REG_EIR, &tx_end);
521 tx_end &= ENC28J60_BIT_EIR_TXIF;
522 } while (!tx_end);
523
524
525 eth_enc28j60_read_reg(dev, ENC28J60_REG_ESTAT, &tx_end);
526
527 k_sem_give(&context->tx_rx_sem);
528
529 if (tx_end & ENC28J60_BIT_ESTAT_TXABRT) {
530 LOG_ERR("%s: TX failed!", dev->name);
531
532 /* 12.1.3 "TRANSMIT ERROR INTERRUPT FLAG (TXERIF)" states:
533 *
534 * "After determining the problem and solution, the
535 * host controller should clear the LATECOL (if set) and
536 * TXABRT bits so that future aborts can be detected
537 * accurately."
538 */
539 eth_enc28j60_clear_eth_reg(dev, ENC28J60_REG_ESTAT,
540 ENC28J60_BIT_ESTAT_TXABRT
541 | ENC28J60_BIT_ESTAT_LATECOL);
542
543 return -EIO;
544 }
545
546 LOG_DBG("%s: Tx successful", dev->name);
547
548 return 0;
549 }
550
enc28j60_read_packet(const struct device * dev,uint16_t frm_len)551 static void enc28j60_read_packet(const struct device *dev, uint16_t frm_len)
552 {
553 const struct eth_enc28j60_config *config = dev->config;
554 struct eth_enc28j60_runtime *context = dev->data;
555 struct net_buf *pkt_buf;
556 struct net_pkt *pkt;
557 uint16_t lengthfr;
558 uint8_t dummy[4];
559
560 /* Get the frame from the buffer */
561 pkt = net_pkt_rx_alloc_with_buffer(get_iface(context), frm_len,
562 AF_UNSPEC, 0, K_MSEC(config->timeout));
563 if (!pkt) {
564 LOG_ERR("%s: Could not allocate rx buffer", dev->name);
565 eth_stats_update_errors_rx(get_iface(context));
566 return;
567 }
568
569 pkt_buf = pkt->buffer;
570 lengthfr = frm_len;
571
572 do {
573 size_t frag_len;
574 uint8_t *data_ptr;
575 size_t spi_frame_len;
576
577 data_ptr = pkt_buf->data;
578
579 /* Review the space available for the new frag */
580 frag_len = net_buf_tailroom(pkt_buf);
581
582 if (frm_len > frag_len) {
583 spi_frame_len = frag_len;
584 } else {
585 spi_frame_len = frm_len;
586 }
587
588 eth_enc28j60_read_mem(dev, data_ptr, spi_frame_len);
589
590 net_buf_add(pkt_buf, spi_frame_len);
591
592 /* One fragment has been written via SPI */
593 frm_len -= spi_frame_len;
594 pkt_buf = pkt_buf->frags;
595 } while (frm_len > 0);
596
597 /* Let's pop the useless CRC */
598 eth_enc28j60_read_mem(dev, dummy, 4);
599
600 /* Pops one padding byte from spi circular buffer
601 * introduced by the device when the frame length is odd
602 */
603 if (lengthfr & 0x01) {
604 eth_enc28j60_read_mem(dev, dummy, 1);
605 }
606
607 net_pkt_set_iface(pkt, context->iface);
608
609 /* Feed buffer frame to IP stack */
610 LOG_DBG("%s: Received packet of length %u", dev->name, lengthfr);
611 if (net_recv_data(net_pkt_iface(pkt), pkt) < 0) {
612 net_pkt_unref(pkt);
613 }
614 }
615
eth_enc28j60_rx(const struct device * dev)616 static int eth_enc28j60_rx(const struct device *dev)
617 {
618 struct eth_enc28j60_runtime *context = dev->data;
619 uint8_t counter;
620
621 /* Errata 6. The Receive Packet Pending Interrupt Flag (EIR.PKTIF)
622 * does not reliably/accurately report the status of pending packet.
623 * Use EPKTCNT register instead.
624 */
625 eth_enc28j60_set_bank(dev, ENC28J60_REG_EPKTCNT);
626 eth_enc28j60_read_reg(dev, ENC28J60_REG_EPKTCNT, &counter);
627 if (!counter) {
628 return 0;
629 }
630
631 k_sem_take(&context->tx_rx_sem, K_FOREVER);
632
633 do {
634 uint16_t frm_len = 0U;
635 uint8_t info[RSV_SIZE];
636 uint16_t next_packet;
637 uint8_t rdptl = 0U;
638 uint8_t rdpth = 0U;
639
640 /* remove read fifo address to packet header address */
641 eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXRDPTL);
642 eth_enc28j60_read_reg(dev, ENC28J60_REG_ERXRDPTL, &rdptl);
643 eth_enc28j60_read_reg(dev, ENC28J60_REG_ERXRDPTH, &rdpth);
644 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERDPTL, rdptl);
645 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERDPTH, rdpth);
646
647 /* Read address for next packet */
648 eth_enc28j60_read_mem(dev, info, 2);
649 next_packet = info[0] | (uint16_t)info[1] << 8;
650
651 /* Errata 14. Even values in ERXRDPT
652 * may corrupt receive buffer.
653 No need adjust next packet
654 if (next_packet == 0) {
655 next_packet = ENC28J60_RXEND;
656 } else if (!(next_packet & 0x01)) {
657 next_packet--;
658 }*/
659
660 /* Read reception status vector */
661 eth_enc28j60_read_mem(dev, info, 4);
662
663 /* Get the frame length from the rx status vector,
664 * minus CRC size at the end which is always present
665 */
666 frm_len = sys_get_le16(info) - 4;
667
668 enc28j60_read_packet(dev, frm_len);
669
670 /* Free buffer memory and decrement rx counter */
671 eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXRDPTL);
672 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXRDPTL,
673 next_packet & 0xFF);
674 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXRDPTH,
675 next_packet >> 8);
676 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_ECON2,
677 ENC28J60_BIT_ECON2_PKTDEC);
678
679 /* Check if there are frames to clean from the buffer */
680 eth_enc28j60_set_bank(dev, ENC28J60_REG_EPKTCNT);
681 eth_enc28j60_read_reg(dev, ENC28J60_REG_EPKTCNT, &counter);
682 } while (counter);
683
684 k_sem_give(&context->tx_rx_sem);
685
686 /* Clear a potential Receive Error Interrupt Flag bit (RX buffer full).
687 * PKTIF was automatically cleared in eth_enc28j60_rx() when EPKTCNT
688 * reached zero, so no need to clear it.
689 */
690 eth_enc28j60_clear_eth_reg(dev, ENC28J60_REG_EIR,
691 ENC28J60_BIT_EIR_RXERIF);
692
693 return 0;
694 }
695
eth_enc28j60_rx_thread(void * p1,void * p2,void * p3)696 static void eth_enc28j60_rx_thread(void *p1, void *p2, void *p3)
697 {
698 ARG_UNUSED(p2);
699 ARG_UNUSED(p3);
700
701 const struct device *dev = p1;
702 struct eth_enc28j60_runtime *context = dev->data;
703 uint8_t int_stat;
704
705 while (true) {
706 k_sem_take(&context->int_sem, K_FOREVER);
707
708 /* Disable interrupts during processing, otherwise there's a small race
709 * window where we can miss one!
710 */
711 eth_enc28j60_clear_eth_reg(dev, ENC28J60_REG_EIE, ENC28J60_BIT_EIE_INTIE);
712
713 eth_enc28j60_read_reg(dev, ENC28J60_REG_EIR, &int_stat);
714 if (int_stat & ENC28J60_BIT_EIR_LINKIF) {
715 uint16_t phir;
716 uint16_t phstat2;
717 /* Clear link change interrupt flag by PHIR reg read */
718 eth_enc28j60_read_phy(dev, ENC28J60_PHY_PHIR, &phir);
719 eth_enc28j60_read_phy(dev, ENC28J60_PHY_PHSTAT2, &phstat2);
720 if (phstat2 & ENC28J60_BIT_PHSTAT2_LSTAT) {
721 LOG_INF("%s: Link up", dev->name);
722 /* We may have been interrupted before L2 init complete
723 * If so flag that the carrier should be set on in init
724 */
725 if (context->iface_initialized) {
726 net_eth_carrier_on(context->iface);
727 } else {
728 context->iface_carrier_on_init = true;
729 }
730 } else {
731 LOG_INF("%s: Link down", dev->name);
732
733 if (context->iface_initialized) {
734 net_eth_carrier_off(context->iface);
735 }
736 }
737 }
738
739 /* We cannot rely on the PKTIF flag because of errata 6. Call
740 * eth_enc28j60_rx() unconditionally. It will check EPKTCNT instead.
741 */
742 eth_enc28j60_rx(dev);
743
744 /* Now that the IRQ line was released, enable interrupts back */
745 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_EIE, ENC28J60_BIT_EIE_INTIE);
746 }
747 }
748
eth_enc28j60_get_capabilities(const struct device * dev)749 static enum ethernet_hw_caps eth_enc28j60_get_capabilities(const struct device *dev)
750 {
751 ARG_UNUSED(dev);
752
753 return ETHERNET_LINK_10BASE_T
754 #if defined(CONFIG_NET_VLAN)
755 | ETHERNET_HW_VLAN
756 #endif
757 ;
758 }
759
eth_enc28j60_iface_init(struct net_if * iface)760 static void eth_enc28j60_iface_init(struct net_if *iface)
761 {
762 const struct device *dev = net_if_get_device(iface);
763 struct eth_enc28j60_runtime *context = dev->data;
764
765 net_if_set_link_addr(iface, context->mac_address,
766 sizeof(context->mac_address),
767 NET_LINK_ETHERNET);
768
769 if (context->iface == NULL) {
770 context->iface = iface;
771 }
772
773 ethernet_init(iface);
774
775 /* The device may have already interrupted us to flag link UP */
776 if (context->iface_carrier_on_init) {
777 net_if_carrier_on(iface);
778 } else {
779 net_if_carrier_off(iface);
780 }
781 context->iface_initialized = true;
782 }
783
784 static const struct ethernet_api api_funcs = {
785 .iface_api.init = eth_enc28j60_iface_init,
786
787 .get_capabilities = eth_enc28j60_get_capabilities,
788 .send = eth_enc28j60_tx,
789 };
790
eth_enc28j60_init(const struct device * dev)791 static int eth_enc28j60_init(const struct device *dev)
792 {
793 const struct eth_enc28j60_config *config = dev->config;
794 struct eth_enc28j60_runtime *context = dev->data;
795
796 /* SPI config */
797 if (!spi_is_ready_dt(&config->spi)) {
798 LOG_ERR("%s: SPI master port %s not ready", dev->name, config->spi.bus->name);
799 return -EINVAL;
800 }
801
802 /* Initialize GPIO */
803 if (!gpio_is_ready_dt(&config->interrupt)) {
804 LOG_ERR("%s: GPIO port %s not ready", dev->name, config->interrupt.port->name);
805 return -EINVAL;
806 }
807
808 if (gpio_pin_configure_dt(&config->interrupt, GPIO_INPUT)) {
809 LOG_ERR("%s: Unable to configure GPIO pin %u", dev->name, config->interrupt.pin);
810 return -EINVAL;
811 }
812
813 gpio_init_callback(&(context->gpio_cb), eth_enc28j60_gpio_callback,
814 BIT(config->interrupt.pin));
815
816 if (gpio_add_callback(config->interrupt.port, &(context->gpio_cb))) {
817 return -EINVAL;
818 }
819
820 gpio_pin_interrupt_configure_dt(&config->interrupt,
821 GPIO_INT_EDGE_TO_ACTIVE);
822
823 if (eth_enc28j60_soft_reset(dev)) {
824 LOG_ERR("%s: Soft-reset failed", dev->name);
825 return -EIO;
826 }
827
828 /* Errata B7/1 */
829 k_busy_wait(D10D24S);
830
831 /* Apply a random MAC address if requested in DT */
832 if (config->random_mac) {
833 gen_random_mac(context->mac_address, MICROCHIP_OUI_B0, MICROCHIP_OUI_B1,
834 MICROCHIP_OUI_B2);
835 LOG_INF("Random MAC Addr %02x:%02x:%02x:%02x:%02x:%02x", context->mac_address[0],
836 context->mac_address[1], context->mac_address[2], context->mac_address[3],
837 context->mac_address[4], context->mac_address[5]);
838 } else {
839 /* Assign octets not previously taken from devicetree */
840 context->mac_address[0] = MICROCHIP_OUI_B0;
841 context->mac_address[1] = MICROCHIP_OUI_B1;
842 context->mac_address[2] = MICROCHIP_OUI_B2;
843 }
844
845 if (eth_enc28j60_init_buffers(dev)) {
846 return -ETIMEDOUT;
847 }
848 eth_enc28j60_init_mac(dev);
849 eth_enc28j60_init_phy(dev);
850
851 /* Enable interruptions */
852 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_EIE, ENC28J60_BIT_EIE_INTIE);
853 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_EIE, ENC28J60_BIT_EIE_PKTIE);
854 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_EIE, ENC28J60_BIT_EIE_LINKIE);
855 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHIE, ENC28J60_BIT_PHIE_PGEIE |
856 ENC28J60_BIT_PHIE_PLNKIE);
857
858 /* Enable Reception */
859 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_ECON1,
860 ENC28J60_BIT_ECON1_RXEN);
861
862 /* Start interruption-poll thread */
863 k_thread_create(&context->thread, context->thread_stack,
864 CONFIG_ETH_ENC28J60_RX_THREAD_STACK_SIZE,
865 eth_enc28j60_rx_thread,
866 (void *)dev, NULL, NULL,
867 K_PRIO_COOP(CONFIG_ETH_ENC28J60_RX_THREAD_PRIO),
868 0, K_NO_WAIT);
869
870 LOG_INF("%s: Initialized", dev->name);
871
872 return 0;
873 }
874
875 #define ENC28J60_DEFINE(inst) \
876 static struct eth_enc28j60_runtime eth_enc28j60_runtime_##inst = { \
877 .mac_address = DT_INST_PROP(inst, local_mac_address), \
878 .tx_rx_sem = \
879 Z_SEM_INITIALIZER((eth_enc28j60_runtime_##inst).tx_rx_sem, 1, UINT_MAX), \
880 .int_sem = Z_SEM_INITIALIZER((eth_enc28j60_runtime_##inst).int_sem, 0, UINT_MAX), \
881 }; \
882 \
883 static const struct eth_enc28j60_config eth_enc28j60_config_##inst = { \
884 .spi = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8), 0), \
885 .interrupt = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \
886 .full_duplex = DT_INST_PROP(0, full_duplex), \
887 .timeout = CONFIG_ETH_ENC28J60_TIMEOUT, \
888 .hw_rx_filter = DT_INST_PROP_OR(inst, hw_rx_filter, ENC28J60_RECEIVE_FILTERS), \
889 .random_mac = DT_INST_PROP(inst, zephyr_random_mac_address), \
890 }; \
891 \
892 ETH_NET_DEVICE_DT_INST_DEFINE(inst, eth_enc28j60_init, NULL, ð_enc28j60_runtime_##inst, \
893 ð_enc28j60_config_##inst, CONFIG_ETH_INIT_PRIORITY, \
894 &api_funcs, NET_ETH_MTU);
895
896 DT_INST_FOREACH_STATUS_OKAY(ENC28J60_DEFINE);
897
