1 /*
2 * SPDX-License-Identifier: Apache-2.0
3 *
4 * Copyright (C) 2022-2023, Intel Corporation
5 *
6 */
7
8 #include <zephyr/drivers/clock_control.h>
9 #include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
10 #include <zephyr/logging/log.h>
11
12 #include "clock_control_agilex5_ll.h"
13
14 #define DT_DRV_COMPAT intel_agilex5_clock
15
16 LOG_MODULE_REGISTER(clock_control_agilex5, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
17
18 struct clock_control_config {
19 DEVICE_MMIO_ROM;
20 };
21
22 struct clock_control_data {
23 DEVICE_MMIO_RAM;
24 };
25
clock_init(const struct device * dev)26 static int clock_init(const struct device *dev)
27 {
28
29 LOG_DBG("Intel Agilex5 clock driver initialized!");
30
31 return 0;
32 }
33
clock_get_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)34 static int clock_get_rate(const struct device *dev, clock_control_subsys_t sub_system,
35 uint32_t *rate)
36 {
37 ARG_UNUSED(dev);
38
39 switch ((intptr_t)sub_system) {
40 case INTEL_SOCFPGA_CLOCK_MPU:
41 *rate = get_mpu_clk();
42 break;
43
44 case INTEL_SOCFPGA_CLOCK_WDT:
45 *rate = get_wdt_clk();
46 break;
47
48 case INTEL_SOCFPGA_CLOCK_UART:
49 *rate = get_uart_clk();
50 break;
51
52 case INTEL_SOCFPGA_CLOCK_MMC:
53 *rate = get_sdmmc_clk();
54 break;
55
56 case INTEL_SOCFPGA_CLOCK_TIMER:
57 *rate = get_timer_clk();
58 break;
59
60 case INTEL_SOCFPGA_CLOCK_QSPI:
61 *rate = get_qspi_clk();
62 break;
63
64 case INTEL_SOCFPGA_CLOCK_I2C:
65 *rate = get_i2c_clk();
66 break;
67
68 case INTEL_SOCFPGA_CLOCK_I3C:
69 *rate = get_i3c_clk();
70 break;
71
72 default:
73 LOG_ERR("Clock ID %ld is not supported\n", (intptr_t)sub_system);
74 return -ENOTSUP;
75 }
76
77 return 0;
78 }
79
80 static DEVICE_API(clock_control, clock_api) = {
81 .get_rate = clock_get_rate,
82 };
83
84 #define CLOCK_CONTROL_DEVICE(_inst) \
85 \
86 static struct clock_control_data clock_control_data_##_inst; \
87 \
88 static const struct clock_control_config clock_control_config_##_inst = { \
89 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(_inst)), \
90 }; \
91 \
92 DEVICE_DT_INST_DEFINE(_inst, clock_init, NULL, &clock_control_data_##_inst, \
93 &clock_control_config_##_inst, PRE_KERNEL_1, \
94 CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_api);
95
96 DT_INST_FOREACH_STATUS_OKAY(CLOCK_CONTROL_DEVICE)
97
