1 /* TI ADS1X1X ADC
2 *
3 * Copyright (c) 2021 Facebook, Inc
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <stdbool.h>
9 #include <zephyr/device.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/adc.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/drivers/i2c.h>
14 #include <zephyr/drivers/gpio.h>
15 #include <zephyr/kernel.h>
16 #include <zephyr/sys/byteorder.h>
17 #include <zephyr/sys/util.h>
18
19 #define ADC_CONTEXT_USES_KERNEL_TIMER
20 #include "adc_context.h"
21
22 LOG_MODULE_REGISTER(ADS1X1X, CONFIG_ADC_LOG_LEVEL);
23
24 #if DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(ti_ads1115, alert_rdy_gpios) || \
25 DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(ti_ads1114, alert_rdy_gpios) || \
26 DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(ti_ads1015, alert_rdy_gpios) || \
27 DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(ti_ads1014, alert_rdy_gpios)
28
29 #define ADC_ADS1X1X_TRIGGER 1
30
31 #endif
32
33 #define ADS1X1X_CONFIG_OS BIT(15)
34 #define ADS1X1X_CONFIG_MUX(x) ((x) << 12)
35 #define ADS1X1X_CONFIG_PGA(x) ((x) << 9)
36 #define ADS1X1X_CONFIG_MODE BIT(8)
37 #define ADS1X1X_CONFIG_DR(x) ((x) << 5)
38 #define ADS1X1X_CONFIG_COMP_MODE BIT(4)
39 #define ADS1X1X_CONFIG_COMP_POL BIT(3)
40 #define ADS1X1X_CONFIG_COMP_LAT BIT(2)
41 #define ADS1X1X_CONFIG_COMP_QUE(x) (x)
42 #define ADS1X1X_THRES_POLARITY_ACTIVE BIT(15)
43
44 enum ads1x1x_reg {
45 ADS1X1X_REG_CONV = 0x00,
46 ADS1X1X_REG_CONFIG = 0x01,
47 ADS1X1X_REG_LO_THRESH = 0x02,
48 ADS1X1X_REG_HI_THRESH = 0x03,
49 };
50
51 enum {
52 ADS1X15_CONFIG_MUX_DIFF_0_1 = 0,
53 ADS1X15_CONFIG_MUX_DIFF_0_3 = 1,
54 ADS1X15_CONFIG_MUX_DIFF_1_3 = 2,
55 ADS1X15_CONFIG_MUX_DIFF_2_3 = 3,
56 ADS1X15_CONFIG_MUX_SINGLE_0 = 4,
57 ADS1X15_CONFIG_MUX_SINGLE_1 = 5,
58 ADS1X15_CONFIG_MUX_SINGLE_2 = 6,
59 ADS1X15_CONFIG_MUX_SINGLE_3 = 7,
60 };
61
62 enum {
63 /* ADS111X, ADS101X samples per second */
64 /* 8, 128 samples per second */
65 ADS1X1X_CONFIG_DR_8_128 = 0,
66 /* 16, 250 samples per second */
67 ADS1X1X_CONFIG_DR_16_250 = 1,
68 /* 32, 490 samples per second */
69 ADS1X1X_CONFIG_DR_32_490 = 2,
70 /* 64, 920 samples per second */
71 ADS1X1X_CONFIG_DR_64_920 = 3,
72 /* 128, 1600 samples per second (default) */
73 ADS1X1X_CONFIG_DR_128_1600 = 4,
74 /* 250, 2400 samples per second */
75 ADS1X1X_CONFIG_DR_250_2400 = 5,
76 /* 475, 3300 samples per second */
77 ADS1X1X_CONFIG_DR_475_3300 = 6,
78 /* 860, 3300 samples per second */
79 ADS1X1X_CONFIG_DR_860_3300 = 7,
80 /* Default data rate */
81 ADS1X1X_CONFIG_DR_DEFAULT = ADS1X1X_CONFIG_DR_128_1600
82 };
83
84 enum {
85 /* +/-6.144V range = Gain 1/3 */
86 ADS1X1X_CONFIG_PGA_6144 = 0,
87 /* +/-4.096V range = Gain 1/2 */
88 ADS1X1X_CONFIG_PGA_4096 = 1,
89 /* +/-2.048V range = Gain 1 (default) */
90 ADS1X1X_CONFIG_PGA_2048 = 2,
91 /* +/-1.024V range = Gain 2 */
92 ADS1X1X_CONFIG_PGA_1024 = 3,
93 /* +/-0.512V range = Gain 4 */
94 ADS1X1X_CONFIG_PGA_512 = 4,
95 /* +/-0.256V range = Gain 8 */
96 ADS1X1X_CONFIG_PGA_256 = 5
97 };
98
99 enum {
100 ADS1X1X_CONFIG_MODE_CONTINUOUS = 0,
101 ADS1X1X_CONFIG_MODE_SINGLE_SHOT = 1,
102 };
103
104 enum {
105 /* Traditional comparator with hysteresis (default) */
106 ADS1X1X_CONFIG_COMP_MODE_TRADITIONAL = 0,
107 /* Window comparator */
108 ADS1X1X_CONFIG_COMP_MODE_WINDOW = 1
109 };
110
111 enum {
112 /* ALERT/RDY pin is low when active (default) */
113 ADS1X1X_CONFIG_COMP_POLARITY_ACTIVE_LO = 0,
114 /* ALERT/RDY pin is high when active */
115 ADS1X1X_CONFIG_COMP_POLARITY_ACTIVE_HI = 1
116 };
117
118 enum {
119 /* Non-latching comparator (default) */
120 ADS1X1X_CONFIG_COMP_NON_LATCHING = 0,
121 /* Latching comparator */
122 ADS1X1X_CONFIG_COMP_LATCHING = 1
123 };
124
125 enum {
126 /* Assert ALERT/RDY after one conversions */
127 ADS1X1X_CONFIG_COMP_QUEUE_1 = 0,
128 /* Assert ALERT/RDY after two conversions */
129 ADS1X1X_CONFIG_COMP_QUEUE_2 = 1,
130 /* Assert ALERT/RDY after four conversions */
131 ADS1X1X_CONFIG_COMP_QUEUE_4 = 2,
132 /* Disable the comparator and put ALERT/RDY in high state (default) */
133 ADS1X1X_CONFIG_COMP_QUEUE_NONE = 3
134 };
135
136 struct ads1x1x_config {
137 struct i2c_dt_spec bus;
138 #ifdef ADC_ADS1X1X_TRIGGER
139 struct gpio_dt_spec alert_rdy;
140 #endif
141 const uint32_t odr_delay[8];
142 uint8_t resolution;
143 bool multiplexer;
144 bool pga;
145 };
146
147 struct ads1x1x_data {
148 const struct device *dev;
149 struct adc_context ctx;
150 k_timeout_t ready_time;
151 struct k_sem acq_sem;
152 int16_t *buffer;
153 int16_t *repeat_buffer;
154 struct k_thread thread;
155 k_tid_t tid;
156 bool differential;
157 #ifdef ADC_ADS1X1X_TRIGGER
158 struct gpio_callback gpio_cb;
159 struct k_work work;
160 #endif
161
162 K_KERNEL_STACK_MEMBER(stack, CONFIG_ADC_ADS1X1X_ACQUISITION_THREAD_STACK_SIZE);
163 };
164
165 #ifdef ADC_ADS1X1X_TRIGGER
ads1x1x_setup_rdy_pin(const struct device * dev,bool enable)166 static inline int ads1x1x_setup_rdy_pin(const struct device *dev, bool enable)
167 {
168 int ret;
169 const struct ads1x1x_config *config = dev->config;
170 gpio_flags_t flags = enable
171 ? GPIO_INPUT | config->alert_rdy.dt_flags
172 : GPIO_DISCONNECTED;
173
174 ret = gpio_pin_configure_dt(&config->alert_rdy, flags);
175 if (ret < 0) {
176 LOG_DBG("Could not configure gpio");
177 }
178 return ret;
179 }
180
ads1x1x_setup_rdy_interrupt(const struct device * dev,bool enable)181 static inline int ads1x1x_setup_rdy_interrupt(const struct device *dev, bool enable)
182 {
183 const struct ads1x1x_config *config = dev->config;
184 gpio_flags_t flags = enable
185 ? GPIO_INT_EDGE_FALLING
186 : GPIO_INT_DISABLE;
187 int32_t ret;
188
189 ret = gpio_pin_interrupt_configure_dt(&config->alert_rdy, flags);
190 if (ret < 0) {
191 LOG_DBG("Could not configure GPIO");
192 }
193 return ret;
194 }
195 #endif
196
ads1x1x_read_reg(const struct device * dev,enum ads1x1x_reg reg_addr,uint16_t * buf)197 static int ads1x1x_read_reg(const struct device *dev, enum ads1x1x_reg reg_addr, uint16_t *buf)
198 {
199 const struct ads1x1x_config *config = dev->config;
200 uint16_t reg_val;
201 int ret;
202
203 ret = i2c_burst_read_dt(&config->bus, reg_addr, (uint8_t *)®_val, sizeof(reg_val));
204 if (ret != 0) {
205 LOG_ERR("ADS1X1X[0x%X]: error reading register 0x%X (%d)", config->bus.addr,
206 reg_addr, ret);
207 return ret;
208 }
209
210 *buf = sys_be16_to_cpu(reg_val);
211
212 return 0;
213 }
214
ads1x1x_write_reg(const struct device * dev,enum ads1x1x_reg reg_addr,uint16_t reg_val)215 static int ads1x1x_write_reg(const struct device *dev, enum ads1x1x_reg reg_addr, uint16_t reg_val)
216 {
217 const struct ads1x1x_config *config = dev->config;
218 uint8_t buf[3];
219 int ret;
220
221 buf[0] = reg_addr;
222 sys_put_be16(reg_val, &buf[1]);
223
224 ret = i2c_write_dt(&config->bus, buf, sizeof(buf));
225
226 if (ret != 0) {
227 LOG_ERR("ADS1X1X[0x%X]: error writing register 0x%X (%d)", config->bus.addr,
228 reg_addr, ret);
229 return ret;
230 }
231
232 return 0;
233 }
234
ads1x1x_start_conversion(const struct device * dev)235 static int ads1x1x_start_conversion(const struct device *dev)
236 {
237 /* send start sampling command */
238 uint16_t config;
239 int ret;
240
241 ret = ads1x1x_read_reg(dev, ADS1X1X_REG_CONFIG, &config);
242 if (ret != 0) {
243 return ret;
244 }
245 config |= ADS1X1X_CONFIG_OS;
246 ret = ads1x1x_write_reg(dev, ADS1X1X_REG_CONFIG, config);
247
248 return ret;
249 }
250
251 #ifdef ADC_ADS1X1X_TRIGGER
252 /* The ALERT/RDY pin can also be configured as a conversion ready
253 * pin. Set the most-significant bit of the Hi_thresh register to 1
254 * and the most-significant bit of Lo_thresh register to 0 to enable
255 * the pin as a conversion ready pin
256 */
ads1x1x_enable_conv_ready_signal(const struct device * dev)257 static int ads1x1x_enable_conv_ready_signal(const struct device *dev)
258 {
259 uint16_t thresh;
260 int rc;
261
262 /* set to 1 to enable conversion ALERT/RDY */
263 rc = ads1x1x_read_reg(dev, ADS1X1X_REG_HI_THRESH, &thresh);
264 if (rc) {
265 return rc;
266 }
267 thresh |= ADS1X1X_THRES_POLARITY_ACTIVE;
268 rc = ads1x1x_write_reg(dev, ADS1X1X_REG_HI_THRESH, thresh);
269 if (rc) {
270 return rc;
271 }
272
273 /* set to 0 to enable conversion ALERT/RDY */
274 rc = ads1x1x_read_reg(dev, ADS1X1X_REG_LO_THRESH, &thresh);
275 if (rc) {
276 return rc;
277 }
278 thresh &= ~ADS1X1X_THRES_POLARITY_ACTIVE;
279 rc = ads1x1x_write_reg(dev, ADS1X1X_REG_LO_THRESH, thresh);
280
281 return rc;
282 }
283 #endif
284
ads1x1x_acq_time_to_dr(const struct device * dev,uint16_t acq_time)285 static inline int ads1x1x_acq_time_to_dr(const struct device *dev, uint16_t acq_time)
286 {
287 struct ads1x1x_data *data = dev->data;
288 const struct ads1x1x_config *ads_config = dev->config;
289 const uint32_t *odr_delay = ads_config->odr_delay;
290 uint32_t odr_delay_us = 0;
291 int odr = -EINVAL;
292 uint16_t acq_value = ADC_ACQ_TIME_VALUE(acq_time);
293
294 /* The ADS1x1x uses samples per seconds units with the lowest being 8SPS
295 * and with acquisition_time only having 14b for time, this will not fit
296 * within here for microsecond units. Use Tick units and allow the user to
297 * specify the ODR directly.
298 */
299 if (acq_time != ADC_ACQ_TIME_DEFAULT && ADC_ACQ_TIME_UNIT(acq_time) != ADC_ACQ_TIME_TICKS) {
300 return -EINVAL;
301 }
302
303 if (acq_time == ADC_ACQ_TIME_DEFAULT) {
304 odr = ADS1X1X_CONFIG_DR_DEFAULT;
305 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_DEFAULT];
306 } else {
307 switch (acq_value) {
308 case ADS1X1X_CONFIG_DR_8_128:
309 odr = ADS1X1X_CONFIG_DR_8_128;
310 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_8_128];
311 break;
312 case ADS1X1X_CONFIG_DR_16_250:
313 odr = ADS1X1X_CONFIG_DR_16_250;
314 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_16_250];
315 break;
316 case ADS1X1X_CONFIG_DR_32_490:
317 odr = ADS1X1X_CONFIG_DR_32_490;
318 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_32_490];
319 break;
320 case ADS1X1X_CONFIG_DR_64_920:
321 odr = ADS1X1X_CONFIG_DR_64_920;
322 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_64_920];
323 break;
324 case ADS1X1X_CONFIG_DR_128_1600:
325 odr = ADS1X1X_CONFIG_DR_128_1600;
326 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_128_1600];
327 break;
328 case ADS1X1X_CONFIG_DR_250_2400:
329 odr = ADS1X1X_CONFIG_DR_250_2400;
330 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_250_2400];
331 break;
332 case ADS1X1X_CONFIG_DR_475_3300:
333 odr = ADS1X1X_CONFIG_DR_475_3300;
334 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_475_3300];
335 break;
336 case ADS1X1X_CONFIG_DR_860_3300:
337 odr = ADS1X1X_CONFIG_DR_860_3300;
338 odr_delay_us = odr_delay[ADS1X1X_CONFIG_DR_860_3300];
339 break;
340 default:
341 break;
342 }
343 }
344
345 /* As per the datasheet, 25us is needed to wake-up from power down mode
346 */
347 odr_delay_us += 25;
348 data->ready_time = K_USEC(odr_delay_us);
349
350 return odr;
351 }
352
ads1x1x_wait_data_ready(const struct device * dev)353 static int ads1x1x_wait_data_ready(const struct device *dev)
354 {
355 int rc;
356 struct ads1x1x_data *data = dev->data;
357
358 k_sleep(data->ready_time);
359 uint16_t status = 0;
360
361 rc = ads1x1x_read_reg(dev, ADS1X1X_REG_CONFIG, &status);
362 if (rc != 0) {
363 return rc;
364 }
365
366 while (!(status & ADS1X1X_CONFIG_OS)) {
367 k_sleep(K_USEC(100));
368 rc = ads1x1x_read_reg(dev, ADS1X1X_REG_CONFIG, &status);
369 if (rc != 0) {
370 return rc;
371 }
372 }
373
374 return rc;
375 }
376
ads1x1x_channel_setup(const struct device * dev,const struct adc_channel_cfg * channel_cfg)377 static int ads1x1x_channel_setup(const struct device *dev,
378 const struct adc_channel_cfg *channel_cfg)
379 {
380 const struct ads1x1x_config *ads_config = dev->config;
381 struct ads1x1x_data *data = dev->data;
382 uint16_t config = 0;
383 int dr = 0;
384
385 if (channel_cfg->channel_id != 0) {
386 LOG_ERR("unsupported channel id '%d'", channel_cfg->channel_id);
387 return -ENOTSUP;
388 }
389
390 if (channel_cfg->reference != ADC_REF_INTERNAL) {
391 LOG_ERR("unsupported channel reference type '%d'", channel_cfg->reference);
392 return -ENOTSUP;
393 }
394
395 if (ads_config->multiplexer) {
396 /* the device has an input multiplexer */
397 if (channel_cfg->differential) {
398 if (channel_cfg->input_positive == 0 && channel_cfg->input_negative == 1) {
399 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_DIFF_0_1);
400 } else if (channel_cfg->input_positive == 0 &&
401 channel_cfg->input_negative == 3) {
402 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_DIFF_0_3);
403 } else if (channel_cfg->input_positive == 1 &&
404 channel_cfg->input_negative == 3) {
405 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_DIFF_1_3);
406 } else if (channel_cfg->input_positive == 2 &&
407 channel_cfg->input_negative == 3) {
408 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_DIFF_2_3);
409 } else {
410 LOG_ERR("unsupported input positive '%d' and input negative '%d'",
411 channel_cfg->input_positive, channel_cfg->input_negative);
412 return -ENOTSUP;
413 }
414 } else {
415 if (channel_cfg->input_positive == 0) {
416 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_SINGLE_0);
417 } else if (channel_cfg->input_positive == 1) {
418 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_SINGLE_1);
419 } else if (channel_cfg->input_positive == 2) {
420 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_SINGLE_2);
421 } else if (channel_cfg->input_positive == 3) {
422 config |= ADS1X1X_CONFIG_MUX(ADS1X15_CONFIG_MUX_SINGLE_3);
423 } else {
424 LOG_ERR("unsupported input positive '%d'",
425 channel_cfg->input_positive);
426 return -ENOTSUP;
427 }
428 }
429 } else {
430 /* only differential supported without multiplexer */
431 if (!((channel_cfg->differential) &&
432 (channel_cfg->input_positive == 0 && channel_cfg->input_negative == 1))) {
433 LOG_ERR("unsupported input positive '%d' and input negative '%d'",
434 channel_cfg->input_positive, channel_cfg->input_negative);
435 return -ENOTSUP;
436 }
437 }
438 /* store differential mode to determine supported resolution */
439 data->differential = channel_cfg->differential;
440
441 dr = ads1x1x_acq_time_to_dr(dev, channel_cfg->acquisition_time);
442 if (dr < 0) {
443 LOG_ERR("unsupported channel acquisition time 0x%02x",
444 channel_cfg->acquisition_time);
445 return -ENOTSUP;
446 }
447
448 config |= ADS1X1X_CONFIG_DR(dr);
449
450 if (ads_config->pga) {
451 /* programmable gain amplifier support */
452 switch (channel_cfg->gain) {
453 case ADC_GAIN_1_3:
454 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_6144);
455 break;
456 case ADC_GAIN_1_2:
457 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_4096);
458 break;
459 case ADC_GAIN_1:
460 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_2048);
461 break;
462 case ADC_GAIN_2:
463 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_1024);
464 break;
465 case ADC_GAIN_4:
466 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_512);
467 break;
468 case ADC_GAIN_8:
469 config |= ADS1X1X_CONFIG_PGA(ADS1X1X_CONFIG_PGA_256);
470 break;
471 default:
472 LOG_ERR("unsupported channel gain '%d'", channel_cfg->gain);
473 return -ENOTSUP;
474 }
475 } else {
476 /* no programmable gain amplifier, so only allow ADC_GAIN_1 */
477 if (channel_cfg->gain != ADC_GAIN_1) {
478 LOG_ERR("unsupported channel gain '%d'", channel_cfg->gain);
479 return -ENOTSUP;
480 }
481 }
482
483 /* Only single shot supported */
484 config |= ADS1X1X_CONFIG_MODE;
485
486 /* disable comparator */
487 config |= ADS1X1X_CONFIG_COMP_MODE;
488
489 return ads1x1x_write_reg(dev, ADS1X1X_REG_CONFIG, config);
490 }
491
ads1x1x_validate_buffer_size(const struct adc_sequence * sequence)492 static int ads1x1x_validate_buffer_size(const struct adc_sequence *sequence)
493 {
494 size_t needed = sizeof(int16_t);
495
496 if (sequence->options) {
497 needed *= (1 + sequence->options->extra_samplings);
498 }
499
500 if (sequence->buffer_size < needed) {
501 return -ENOMEM;
502 }
503
504 return 0;
505 }
506
ads1x1x_validate_sequence(const struct device * dev,const struct adc_sequence * sequence)507 static int ads1x1x_validate_sequence(const struct device *dev, const struct adc_sequence *sequence)
508 {
509 const struct ads1x1x_config *config = dev->config;
510 struct ads1x1x_data *data = dev->data;
511 uint8_t resolution = data->differential ? config->resolution : config->resolution - 1;
512 int err;
513
514 if (sequence->resolution != resolution) {
515 LOG_ERR("unsupported resolution %d", sequence->resolution);
516 return -ENOTSUP;
517 }
518
519 if (sequence->channels != BIT(0)) {
520 LOG_ERR("only channel 0 supported");
521 return -ENOTSUP;
522 }
523
524 if (sequence->oversampling) {
525 LOG_ERR("oversampling not supported");
526 return -ENOTSUP;
527 }
528
529 err = ads1x1x_validate_buffer_size(sequence);
530 if (err) {
531 LOG_ERR("buffer size too small");
532 return -ENOTSUP;
533 }
534
535 return 0;
536 }
537
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)538 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
539 {
540 struct ads1x1x_data *data = CONTAINER_OF(ctx, struct ads1x1x_data, ctx);
541
542 if (repeat_sampling) {
543 data->buffer = data->repeat_buffer;
544 }
545 }
546
adc_context_start_sampling(struct adc_context * ctx)547 static void adc_context_start_sampling(struct adc_context *ctx)
548 {
549 struct ads1x1x_data *data = CONTAINER_OF(ctx, struct ads1x1x_data, ctx);
550 int ret;
551
552 data->repeat_buffer = data->buffer;
553
554 ret = ads1x1x_start_conversion(data->dev);
555 if (ret != 0) {
556 /* if we fail to complete the I2C operations to start
557 * sampling, return an immediate error (likely -EIO) rather
558 * than handing it off to the acquisition thread.
559 */
560 adc_context_complete(ctx, ret);
561 return;
562 }
563
564 /* Give semaphore only if the thread is running */
565 if (data->tid) {
566 k_sem_give(&data->acq_sem);
567 }
568 }
569
ads1x1x_adc_start_read(const struct device * dev,const struct adc_sequence * sequence)570 static int ads1x1x_adc_start_read(const struct device *dev, const struct adc_sequence *sequence)
571 {
572 int rc;
573 struct ads1x1x_data *data = dev->data;
574
575 rc = ads1x1x_validate_sequence(dev, sequence);
576 if (rc != 0) {
577 return rc;
578 }
579
580 data->buffer = sequence->buffer;
581
582 #ifdef ADC_ADS1X1X_TRIGGER
583 const struct ads1x1x_config *config = dev->config;
584
585 if (config->alert_rdy.port) {
586 rc = ads1x1x_setup_rdy_pin(dev, true);
587 if (rc < 0) {
588 LOG_ERR("Could not configure GPIO Alert/RDY");
589 return rc;
590 }
591 rc = ads1x1x_setup_rdy_interrupt(dev, true);
592 if (rc < 0) {
593 LOG_ERR("Could not configure Alert/RDY interrupt");
594 return rc;
595 }
596 }
597 #endif
598
599 adc_context_start_read(&data->ctx, sequence);
600
601 return adc_context_wait_for_completion(&data->ctx);
602 }
603
ads1x1x_adc_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)604 static int ads1x1x_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
605 struct k_poll_signal *async)
606 {
607 int rc;
608 struct ads1x1x_data *data = dev->data;
609
610 adc_context_lock(&data->ctx, async ? true : false, async);
611 rc = ads1x1x_adc_start_read(dev, sequence);
612 adc_context_release(&data->ctx, rc);
613
614 return rc;
615 }
616
ads1x1x_adc_perform_read(const struct device * dev)617 static int ads1x1x_adc_perform_read(const struct device *dev)
618 {
619 int rc;
620 struct ads1x1x_data *data = dev->data;
621 const struct ads1x1x_config *config = dev->config;
622 int16_t buf;
623
624 rc = ads1x1x_read_reg(dev, ADS1X1X_REG_CONV, &buf);
625 if (rc != 0) {
626 adc_context_complete(&data->ctx, rc);
627 return rc;
628 }
629 /* The ads101x stores it's 12b data in the upper part
630 * while the ads111x uses all 16b in the register, so
631 * shift down. Data is also signed, so perform
632 * division rather than shifting
633 */
634 *data->buffer++ = buf / (1 << (16 - config->resolution));
635
636 adc_context_on_sampling_done(&data->ctx, dev);
637
638 return rc;
639 }
640
ads1x1x_read(const struct device * dev,const struct adc_sequence * sequence)641 static int ads1x1x_read(const struct device *dev, const struct adc_sequence *sequence)
642 {
643 return ads1x1x_adc_read_async(dev, sequence, NULL);
644 }
645
ads1x1x_acquisition_thread(void * p1,void * p2,void * p3)646 static void ads1x1x_acquisition_thread(void *p1, void *p2, void *p3)
647 {
648 ARG_UNUSED(p2);
649 ARG_UNUSED(p3);
650
651 const struct device *dev = p1;
652 struct ads1x1x_data *data = dev->data;
653 int rc;
654
655 while (true) {
656 k_sem_take(&data->acq_sem, K_FOREVER);
657
658 rc = ads1x1x_wait_data_ready(dev);
659 if (rc != 0) {
660 LOG_ERR("failed to get ready status (err %d)", rc);
661 adc_context_complete(&data->ctx, rc);
662 continue;
663 }
664
665 ads1x1x_adc_perform_read(dev);
666 }
667 }
668
669 #ifdef ADC_ADS1X1X_TRIGGER
ads1x1x_work_fn(struct k_work * work)670 static void ads1x1x_work_fn(struct k_work *work)
671 {
672 struct ads1x1x_data *data;
673 const struct device *dev;
674
675 data = CONTAINER_OF(work, struct ads1x1x_data, work);
676 dev = data->dev;
677
678 ads1x1x_adc_perform_read(dev);
679 }
680
ads1x1x_conv_ready_cb(const struct device * gpio_dev,struct gpio_callback * cb,uint32_t pins)681 static void ads1x1x_conv_ready_cb(const struct device *gpio_dev,
682 struct gpio_callback *cb,
683 uint32_t pins)
684 {
685 struct ads1x1x_data *data;
686 const struct device *dev;
687 const struct ads1x1x_config *config;
688 int rc;
689
690 ARG_UNUSED(gpio_dev);
691
692 data = CONTAINER_OF(cb, struct ads1x1x_data, gpio_cb);
693 dev = data->dev;
694 config = dev->config;
695
696 if (config->alert_rdy.port) {
697 rc = ads1x1x_setup_rdy_pin(dev, false);
698 if (rc < 0) {
699 return;
700 }
701 rc = ads1x1x_setup_rdy_interrupt(dev, false);
702 if (rc < 0) {
703 return;
704 }
705 }
706
707 /* Execute outside of the ISR context */
708 k_work_submit(&data->work);
709 }
710
ads1x1x_init_interrupt(const struct device * dev)711 static int ads1x1x_init_interrupt(const struct device *dev)
712 {
713 const struct ads1x1x_config *config = dev->config;
714 struct ads1x1x_data *data = dev->data;
715 int rc;
716
717 /* Disable the interrupt */
718 rc = ads1x1x_setup_rdy_pin(dev, false);
719 if (rc < 0) {
720 LOG_ERR("Could disable the alert/rdy gpio pin.");
721 return rc;
722 }
723 rc = ads1x1x_setup_rdy_interrupt(dev, false);
724 if (rc < 0) {
725 LOG_ERR("Could disable the alert/rdy interrupts.");
726 return rc;
727 }
728 gpio_init_callback(&data->gpio_cb, ads1x1x_conv_ready_cb,
729 BIT(config->alert_rdy.pin));
730 rc = gpio_add_callback(config->alert_rdy.port, &data->gpio_cb);
731 if (rc) {
732 LOG_ERR("Could not set gpio callback.");
733 return -rc;
734 }
735
736 /* Use the interruption generated by the pin RDY */
737 k_work_init(&data->work, ads1x1x_work_fn);
738
739 rc = ads1x1x_enable_conv_ready_signal(dev);
740 if (rc) {
741 LOG_ERR("failed to configure ALERT/RDY pin (err=%d)", rc);
742 return rc;
743 }
744
745 return 0;
746 }
747 #endif
748
ads1x1x_init(const struct device * dev)749 static int ads1x1x_init(const struct device *dev)
750 {
751 const struct ads1x1x_config *config = dev->config;
752 struct ads1x1x_data *data = dev->data;
753
754 data->dev = dev;
755
756 k_sem_init(&data->acq_sem, 0, 1);
757
758 if (!device_is_ready(config->bus.bus)) {
759 LOG_ERR("I2C bus %s not ready", config->bus.bus->name);
760 return -ENODEV;
761 }
762
763 #ifdef ADC_ADS1X1X_TRIGGER
764 if (config->alert_rdy.port) {
765 if (ads1x1x_init_interrupt(dev) < 0) {
766 LOG_ERR("Failed to initialize interrupt.");
767 return -EIO;
768 }
769 } else
770 #endif
771 {
772 LOG_DBG("Using acquisition thread");
773
774 data->tid =
775 k_thread_create(&data->thread, data->stack,
776 K_THREAD_STACK_SIZEOF(data->stack),
777 (k_thread_entry_t)ads1x1x_acquisition_thread,
778 (void *)dev, NULL, NULL,
779 CONFIG_ADC_ADS1X1X_ACQUISITION_THREAD_PRIO,
780 0, K_NO_WAIT);
781 k_thread_name_set(data->tid, "adc_ads1x1x");
782 }
783
784 adc_context_unlock_unconditionally(&data->ctx);
785
786 return 0;
787 }
788
789 static DEVICE_API(adc, ads1x1x_api) = {
790 .channel_setup = ads1x1x_channel_setup,
791 .read = ads1x1x_read,
792 .ref_internal = 2048,
793 #ifdef CONFIG_ADC_ASYNC
794 .read_async = ads1x1x_adc_read_async,
795 #endif
796 };
797
798 #define DT_INST_ADS1X1X(inst, t) DT_INST(inst, ti_ads##t)
799
800 #define ADS1X1X_RDY_PROPS(n) \
801 .alert_rdy = GPIO_DT_SPEC_INST_GET_OR(n, alert_rdy_gpios, {0}), \
802
803 #define ADS1X1X_RDY(t, n) \
804 IF_ENABLED(DT_NODE_HAS_PROP(DT_INST_ADS1X1X(n, t), alert_rdy_gpios), \
805 (ADS1X1X_RDY_PROPS(n)))
806
807 #define ADS1X1X_INIT(t, n, odr_delay_us, res, mux, pgab) \
808 static const struct ads1x1x_config ads##t##_config_##n = { \
809 .bus = I2C_DT_SPEC_GET(DT_INST_ADS1X1X(n, t)), \
810 .odr_delay = odr_delay_us, \
811 .resolution = res, \
812 .multiplexer = mux, \
813 .pga = pgab, \
814 IF_ENABLED(ADC_ADS1X1X_TRIGGER, (ADS1X1X_RDY(t, n))) \
815 }; \
816 static struct ads1x1x_data ads##t##_data_##n = { \
817 ADC_CONTEXT_INIT_LOCK(ads##t##_data_##n, ctx), \
818 ADC_CONTEXT_INIT_TIMER(ads##t##_data_##n, ctx), \
819 ADC_CONTEXT_INIT_SYNC(ads##t##_data_##n, ctx), \
820 }; \
821 DEVICE_DT_DEFINE(DT_INST_ADS1X1X(n, t), ads1x1x_init, NULL, &ads##t##_data_##n, \
822 &ads##t##_config_##n, POST_KERNEL, CONFIG_ADC_ADS1X1X_INIT_PRIORITY, \
823 &ads1x1x_api);
824
825 /* The ADS111X provides 16 bits of data in binary two's complement format
826 * A positive full-scale (+FS) input produces an output code of 7FFFh and a
827 * negative full-scale (–FS) input produces an output code of 8000h. Single
828 * ended signal measurements only use the positive code range from
829 * 0000h to 7FFFh
830 */
831 #define ADS111X_RESOLUTION 16
832
833 /*
834 * Approximated ADS111x acquisition times in microseconds. These are
835 * used for the initial delay when polling for data ready.
836 * {8 SPS, 16 SPS, 32 SPS, 64 SPS, 128 SPS (default), 250 SPS, 475 SPS, 860 SPS}
837 */
838 #define ADS111X_ODR_DELAY_US \
839 { \
840 125000, 62500, 31250, 15625, 7813, 4000, 2105, 1163 \
841 }
842
843 /*
844 * ADS1115: 16 bit, multiplexer, programmable gain amplifier
845 */
846 #define ADS1115_INIT(n) ADS1X1X_INIT(1115, n, ADS111X_ODR_DELAY_US, ADS111X_RESOLUTION, true, true)
847 #undef DT_DRV_COMPAT
848 #define DT_DRV_COMPAT ti_ads1115
849 DT_INST_FOREACH_STATUS_OKAY(ADS1115_INIT)
850
851 /*
852 * ADS1114: 16 bit, no multiplexer, programmable gain amplifier
853 */
854 #define ADS1114_INIT(n) ADS1X1X_INIT(1114, n, ADS111X_ODR_DELAY_US, ADS111X_RESOLUTION, false, true)
855 #undef DT_DRV_COMPAT
856 #define DT_DRV_COMPAT ti_ads1114
857 DT_INST_FOREACH_STATUS_OKAY(ADS1114_INIT)
858
859 /*
860 * ADS1113: 16 bit, no multiplexer, no programmable gain amplifier
861 */
862 #define ADS1113_INIT(n) \
863 ADS1X1X_INIT(1113, n, ADS111X_ODR_DELAY_US, ADS111X_RESOLUTION, false, false)
864 #undef DT_DRV_COMPAT
865 #define DT_DRV_COMPAT ti_ads1113
866 DT_INST_FOREACH_STATUS_OKAY(ADS1113_INIT)
867
868 /* The ADS101X provides 12 bits of data in binary two's complement format
869 * A positive full-scale (+FS) input produces an output code of 7FFh and a
870 * negative full-scale (–FS) input produces an output code of 800h. Single
871 * ended signal measurements only use the positive code range from
872 * 000h to 7FFh
873 */
874 #define ADS101X_RESOLUTION 12
875
876 /*
877 * Approximated ADS101x acquisition times in microseconds. These are
878 * used for the initial delay when polling for data ready.
879 * {128 SPS, 250 SPS, 490 SPS, 920 SPS, 1600 SPS (default), 2400 SPS, 3300 SPS, 3300 SPS}
880 */
881 #define ADS101X_ODR_DELAY_US \
882 { \
883 7813, 4000, 2041, 1087, 625, 417, 303, 303 \
884 }
885
886 /*
887 * ADS1015: 12 bit, multiplexer, programmable gain amplifier
888 */
889 #define ADS1015_INIT(n) ADS1X1X_INIT(1015, n, ADS101X_ODR_DELAY_US, ADS101X_RESOLUTION, true, true)
890 #undef DT_DRV_COMPAT
891 #define DT_DRV_COMPAT ti_ads1015
892 DT_INST_FOREACH_STATUS_OKAY(ADS1015_INIT)
893
894 /*
895 * ADS1014: 12 bit, no multiplexer, programmable gain amplifier
896 */
897 #define ADS1014_INIT(n) ADS1X1X_INIT(1014, n, ADS101X_ODR_DELAY_US, ADS101X_RESOLUTION, false, true)
898 #undef DT_DRV_COMPAT
899 #define DT_DRV_COMPAT ti_ads1014
900 DT_INST_FOREACH_STATUS_OKAY(ADS1014_INIT)
901
902 /*
903 * ADS1013: 12 bit, no multiplexer, no programmable gain amplifier
904 */
905 #define ADS1013_INIT(n) \
906 ADS1X1X_INIT(1013, n, ADS101X_ODR_DELAY_US, ADS101X_RESOLUTION, false, false)
907 #undef DT_DRV_COMPAT
908 #define DT_DRV_COMPAT ti_ads1013
909 DT_INST_FOREACH_STATUS_OKAY(ADS1013_INIT)
910
