1# ADC configuration options
2
3# Copyright (c) 2015 Intel Corporation
4# SPDX-License-Identifier: Apache-2.0
5
6config ADC_MCUX_ADC12
7	bool "MCUX ADC12 driver"
8	default y
9	depends on DT_HAS_NXP_ADC12_ENABLED
10	select PINCTRL
11	help
12	  Enable the MCUX ADC12 driver.
13
14config ADC_MCUX_ADC16
15	bool "MCUX ADC16 driver"
16	default y
17	depends on DT_HAS_NXP_KINETIS_ADC16_ENABLED
18	select PINCTRL
19	help
20	  Enable the MCUX ADC16 driver.
21
22config ADC_MCUX_12B1MSPS_SAR
23	bool "MCUX 12B1MSPS SAR ADC driver"
24	default y
25	select PINCTRL
26	depends on DT_HAS_NXP_MCUX_12B1MSPS_SAR_ENABLED
27	help
28	  Enable the MCUX 12B1MSPS SAR ADC driver.
29
30config ADC_MCUX_LPADC
31	bool "MCUX LPADC driver"
32	default y
33	select ADC_CONFIGURABLE_INPUTS
34	select REGULATOR
35	select PINCTRL
36	depends on DT_HAS_NXP_LPC_LPADC_ENABLED
37	help
38	  Enable the MCUX LPADC driver.
39
40if ADC_MCUX_12B1MSPS_SAR || ADC_MCUX_LPADC
41config ADC_MCUX_ETC
42	bool "MCUX ADC ETC driver"
43	depends on HAS_MCUX_ADC_ETC
44	help
45	  Enable the MCUX ADC ETC driver.
46endif
47
48config ADC_MCUX_GAU
49	bool "MCUX GAU ADC driver"
50	default y
51	depends on DT_HAS_NXP_GAU_ADC_ENABLED
52	select ADC_CONFIGURABLE_INPUTS
53	help
54	  Enable the GAU ADC driver
55
56if ADC_MCUX_ADC16
57
58choice
59	prompt "Clock Divide Selection"
60	default ADC_MCUX_ADC16_CLK_DIV_RATIO_1
61
62config ADC_MCUX_ADC16_CLK_DIV_RATIO_1
63	bool "Divide ratio is 1"
64
65config ADC_MCUX_ADC16_CLK_DIV_RATIO_2
66	bool "Divide ratio is 2"
67
68config ADC_MCUX_ADC16_CLK_DIV_RATIO_4
69	bool "Divide ratio is 4"
70
71config ADC_MCUX_ADC16_CLK_DIV_RATIO_8
72	bool "Divide ratio is 8"
73
74endchoice
75
76choice ADC_MCUX_ADC16_VREF
77	prompt "Voltage Reference Selection"
78	default ADC_MCUX_ADC16_VREF_DEFAULT
79
80config ADC_MCUX_ADC16_VREF_DEFAULT
81	bool "Default voltage reference pair V_REFH and V_REFL"
82
83config ADC_MCUX_ADC16_VREF_ALTERNATE
84	bool "Alternate reference pair"
85
86endchoice
87
88config ADC_MCUX_ADC16_ENABLE_EDMA
89	bool "EDMA for adc driver"
90	depends on HAS_MCUX_ADC16 && HAS_MCUX_EDMA
91	help
92	  Enable the MCUX ADC16 driver.
93
94if ADC_MCUX_ADC16_ENABLE_EDMA
95
96config ADC_MCUX_ADC16_HW_TRIGGER
97	bool "ADC HW TRIGGER"
98	default y
99	help
100	  Support HW Trigger ADC
101
102endif # ADC_MCUX_ADC16_ENABLE_EDMA
103
104endif # ADC_MCUX_ADC16
105
106
107if ADC_MCUX_LPADC
108
109config LPADC_DO_OFFSET_CALIBRATION
110	bool "Do offset calibration"
111	help
112	  Do offset calibration
113
114config LPADC_CHANNEL_COUNT
115	int "LPADC channel count"
116	default 15
117	range 1 15
118	help
119	  Amount of hardware command channels to use, reduce to save RAM.
120	  The user can reduce this value if their application uses fewer than
121	  15 ADC channels. This value corresponds to how many of the CMD
122	  registers can be configured within the ADC.
123
124
125endif # ADC_MCUX_LPADC
126