1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 1, 13)>,
10				<NRF_PSEL(UART_RX, 0, 29)>,
11				<NRF_PSEL(UART_RTS, 0, 31)>,
12				<NRF_PSEL(UART_CTS, 1, 12)>;
13		};
14	};
15
16	uart0_sleep: uart0_sleep {
17		group1 {
18			psels = <NRF_PSEL(UART_TX, 1, 13)>,
19				<NRF_PSEL(UART_RX, 0, 29)>,
20				<NRF_PSEL(UART_RTS, 0, 31)>,
21				<NRF_PSEL(UART_CTS, 1, 12)>;
22			low-power-enable;
23		};
24	};
25
26	i2c0_default: i2c0_default {
27		group1 {
28			psels = <NRF_PSEL(TWIM_SDA, 0, 16)>,
29				<NRF_PSEL(TWIM_SCL, 0, 24)>;
30		};
31	};
32
33	i2c0_sleep: i2c0_sleep {
34		group1 {
35			psels = <NRF_PSEL(TWIM_SDA, 0, 16)>,
36				<NRF_PSEL(TWIM_SCL, 0, 24)>;
37			low-power-enable;
38		};
39	};
40
41	spi0_default: spi0_default {
42		group1 {
43			psels = <NRF_PSEL(SPIM_SCK, 0, 7)>,
44				<NRF_PSEL(SPIM_MOSI, 1, 0)>,
45				<NRF_PSEL(SPIM_MISO, 0, 15)>;
46		};
47	};
48
49	spi0_sleep: spi0_sleep {
50		group1 {
51			psels = <NRF_PSEL(SPIM_SCK, 0, 7)>,
52				<NRF_PSEL(SPIM_MOSI, 1, 0)>,
53				<NRF_PSEL(SPIM_MISO, 0, 15)>;
54			low-power-enable;
55		};
56	};
57
58	spi1_default: spi1_default {
59		group1 {
60			psels = <NRF_PSEL(SPIM_SCK, 0, 3)>,
61				<NRF_PSEL(SPIM_MOSI, 0, 28)>,
62				<NRF_PSEL(SPIM_MISO, 0, 9)>;
63		};
64	};
65
66	spi1_sleep: spi1_sleep {
67		group1 {
68			psels = <NRF_PSEL(SPIM_SCK, 0, 3)>,
69				<NRF_PSEL(SPIM_MOSI, 0, 28)>,
70				<NRF_PSEL(SPIM_MISO, 0, 9)>;
71			low-power-enable;
72		};
73	};
74
75	pwm0_default: pwm0_default {
76		group1 {
77			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>,
78				<NRF_PSEL(PWM_OUT1, 1, 0)>,
79				<NRF_PSEL(PWM_OUT2, 0, 25)>;
80			nordic,invert;
81		};
82	};
83
84	pwm0_sleep: pwm0_sleep {
85		group1 {
86			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>,
87				<NRF_PSEL(PWM_OUT1, 1, 0)>,
88				<NRF_PSEL(PWM_OUT2, 0, 25)>;
89			low-power-enable;
90		};
91	};
92
93};
94