1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 6)>,
10				<NRF_PSEL(UART_RX, 0, 8)>,
11				<NRF_PSEL(UART_RTS, 0, 5)>,
12				<NRF_PSEL(UART_CTS, 0, 7)>;
13		};
14	};
15
16	uart0_sleep: uart0_sleep {
17		group1 {
18			psels = <NRF_PSEL(UART_TX, 0, 6)>,
19				<NRF_PSEL(UART_RX, 0, 8)>,
20				<NRF_PSEL(UART_RTS, 0, 5)>,
21				<NRF_PSEL(UART_CTS, 0, 7)>;
22			low-power-enable;
23		};
24	};
25
26	i2c0_default: i2c0_default {
27		group1 {
28			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
29				<NRF_PSEL(TWIM_SCL, 0, 27)>;
30		};
31	};
32
33	i2c0_sleep: i2c0_sleep {
34		group1 {
35			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
36				<NRF_PSEL(TWIM_SCL, 0, 27)>;
37			low-power-enable;
38		};
39	};
40
41	pwm0_default: pwm0_default {
42		group1 {
43			psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
44			nordic,invert;
45		};
46	};
47
48	pwm0_sleep: pwm0_sleep {
49		group1 {
50			psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
51			low-power-enable;
52		};
53	};
54
55	spi0_default: spi0_default {
56		group1 {
57			psels = <NRF_PSEL(SPIM_SCK, 0, 25)>,
58				<NRF_PSEL(SPIM_MOSI, 0, 23)>,
59				<NRF_PSEL(SPIM_MISO, 0, 24)>;
60		};
61	};
62
63	spi0_sleep: spi0_sleep {
64		group1 {
65			psels = <NRF_PSEL(SPIM_SCK, 0, 25)>,
66				<NRF_PSEL(SPIM_MOSI, 0, 23)>,
67				<NRF_PSEL(SPIM_MISO, 0, 24)>;
68			low-power-enable;
69		};
70	};
71
72};
73