1/*
2 * Copyright (c) 2024 Jerónimo Agulló <jeronimoagullo97@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8#include <nordic/nrf52840_qiaa.dtsi>
9#include "micromod_nrf52840-pinctrl.dtsi"
10#include <zephyr/dt-bindings/input/input-event-codes.h>
11
12/ {
13	model = "Sparkfun Micrmod nRF52840 board";
14	compatible = "sparkfun,micromod-nrf52840";
15
16	chosen {
17		zephyr,console = &uart0;
18		zephyr,sram = &sram0;
19		zephyr,flash = &flash0;
20		zephyr,code-partition = &slot0_partition;
21		zephyr,ieee802154 = &ieee802154;
22	};
23
24	/* These aliases are provided for compatibility with samples */
25	aliases {
26		led0 = &led0;
27		watchdog0 = &wdt0;
28	};
29
30	leds {
31		compatible = "gpio-leds";
32		led0: led_0 {
33			gpios = <&gpio0 13 0>;
34			label = "Blue LED";
35		};
36	};
37
38	micromod_header: connector {
39		compatible = "sparkfun,micromod-gpio";
40		#gpio-cells = <2>;
41		gpio-map-mask = <0xffffffff 0xffffffc0>;
42		gpio-map-pass-thru = <0 0x3f>;
43		gpio-map = <0 0 &gpio0 4 0>,	/* A0 */
44			   <1 0 &gpio0 5 0>,	/* A1 */
45			   <2 0 &gpio0 27 0>,	/* D0 */
46			   <3 0 &gpio1 8 0>,	/* D1/CAM_TRIG */
47			   <4 0 &gpio0 15 0>,	/* I2C_INT# */
48			   <5 0 &gpio0 29 0>,	/* G0/BUS0 */
49			   <6 0 &gpio0 3 0>,	/* G1/BUS1 */
50			   <7 0 &gpio1 13 0>,	/* G2/BUS2 */
51			   <8 0 &gpio1 12 0>,	/* G3/BUS3 */
52			   <9 0 &gpio1 11 0>,	/* G4/BUS4 */
53			   <10 0 &gpio0 17 0>,	/* G5/BUS5 */
54			   <11 0 &gpio1 6 0>,	/* G6/BUS6 */
55			   <12 0 &gpio1 4 0>,	/* G7/BUS7 */
56			   <13 0 &gpio1 14 0>,	/* G8 */
57			   <14 0 &gpio0 9 0>,	/* G9/ADC_D-/CAM_HSYNC */
58			   <15 0 &gpio0 10 0>,	/* G10/ADC_D+/CAM_VSYNC */
59			   //<16 NO CONNECTED	/* G11/SWO */
60			   <17 0 &gpio0 20 0>;	/* SPI_CS */
61	};
62};
63
64&reg0 {
65	status = "okay";
66};
67
68&reg1 {
69	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
70};
71
72&adc {
73	status = "okay";
74};
75
76&gpiote {
77	status = "okay";
78};
79
80&gpio0 {
81	status = "okay";
82};
83
84&gpio1 {
85	status = "okay";
86};
87
88&uicr {
89	nfct-pins-as-gpios;
90	gpio-as-nreset;
91};
92
93&uart0 {
94	compatible = "nordic,nrf-uarte";
95	current-speed = <115200>;
96	status = "okay";
97	pinctrl-0 = <&uart0_default>;
98	pinctrl-1 = <&uart0_sleep>;
99	pinctrl-names = "default", "sleep";
100};
101
102&uart1 {
103	compatible = "nordic,nrf-uarte";
104	current-speed = <115200>;
105	status = "okay";
106	pinctrl-0 = <&uart1_default>;
107	pinctrl-1 = <&uart1_sleep>;
108	pinctrl-names = "default", "sleep";
109};
110
111&i2c0 {
112	compatible = "nordic,nrf-twi";
113	status = "okay";
114	pinctrl-0 = <&i2c0_default>;
115	pinctrl-1 = <&i2c0_sleep>;
116	pinctrl-names = "default", "sleep";
117};
118
119&i2c1 {
120	compatible = "nordic,nrf-twi";
121	status = "okay";
122	pinctrl-0 = <&i2c1_default>;
123	pinctrl-1 = <&i2c1_sleep>;
124	pinctrl-names = "default", "sleep";
125};
126
127&spi2 {
128	compatible = "nordic,nrf-spi";
129	status = "okay";
130	cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
131	pinctrl-0 = <&spi0_default>;
132	pinctrl-1 = <&spi0_sleep>;
133	pinctrl-names = "default", "sleep";
134};
135
136&qspi {
137	status = "okay";
138	pinctrl-0 = <&qspi_default>;
139	pinctrl-1 = <&qspi_sleep>;
140	pinctrl-names = "default", "sleep";
141	w25q128jv: w25q128jv@0 {
142		status="okay";
143		compatible = "nordic,qspi-nor";
144		reg = <0>;
145		writeoc = "pp4io";
146		readoc = "read4io";
147		sck-frequency = <DT_FREQ_M(32)>;
148		jedec-id = [ef 70 18];
149		size = <DT_SIZE_M(128)>;
150		has-dpd;
151		t-enter-dpd = <3000>;
152		t-exit-dpd = <3000>;
153	};
154};
155
156&ieee802154 {
157	status = "okay";
158};
159
160&flash0 {
161
162	partitions {
163		compatible = "fixed-partitions";
164		#address-cells = <1>;
165		#size-cells = <1>;
166
167		boot_partition: partition@0 {
168			label = "mcuboot";
169			reg = <0x00000000 0x00010000>;
170		};
171		slot0_partition: partition@10000 {
172			label = "image-0";
173			reg = <0x00010000 0x00076000>;
174		};
175
176		slot1_partition: partition@86000 {
177			label = "image-1";
178			reg = <0x00086000 0x00074000>;
179		};
180
181		/*
182		 * The flash starting at 0x000f8000 and ending at
183		 * 0x000fffff is reserved for use by the application.
184		 */
185
186		/*
187		 * Storage partition will be used by FCB/LittleFS/NVS
188		 * if enabled.
189		 */
190
191		storage_partition: partition@fA000 {
192			label = "storage";
193			reg = <0x000fA000 0x00006000>;
194		};
195	};
196};
197
198zephyr_udc0: &usbd {
199	compatible = "nordic,nrf-usbd";
200	status = "okay";
201};
202
203// Sparkfun Micromod compatible pins
204micromod_1_uart: &uart0 {};
205micromod_2_uart: &uart1 {};
206micromod_0_i2c: &i2c0 {};
207micromod_1_i2c: &i2c1 {};
208micromod_0_spi: &spi2 {};
209