1 /*
2  * Copyright (c) 2023 Synopsys
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/arch/cpu.h>
8 #include <zephyr/init.h>
9 
10 #define DFSS_SPI0_BASE			0x80010000
11 #define DFSS_SPI1_BASE			0x80010100
12 #define REG_CLK_ENA_OFFSET		(0x16)  /* DFSS only */
13 
14 /* Enable clock for DFSS SPI0 controller & DFSS SPI1 controller */
emsdp_dfss_clock_init(void)15 static int emsdp_dfss_clock_init(void)
16 {
17 	sys_out32(1, DFSS_SPI0_BASE + REG_CLK_ENA_OFFSET);
18 	sys_out32(1, DFSS_SPI1_BASE + REG_CLK_ENA_OFFSET);
19 
20 	return 0;
21 }
22 
23 SYS_INIT(emsdp_dfss_clock_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
24