1 /*
2  * Copyright (c) 2019 Interay Solutions B.V.
3  * Copyright (c) 2019 Oane Kingma
4  * Copyright (c) 2020 Thorvald Natvig
5  *
6  * SPDX-License-Identifier: Apache-2.0
7  */
8 
9 #include <zephyr/init.h>
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/sys/printk.h>
12 #include "em_cmu.h"
13 #include "board.h"
14 
efm32gg_slwstk6121a_init(void)15 static int efm32gg_slwstk6121a_init(void)
16 {
17 
18 	const struct device *cur_dev;
19 
20 	/* Configure ethernet reference clock */
21 	cur_dev = DEVICE_DT_GET(ETH_REF_CLK_GPIO_NODE);
22 	if (!device_is_ready(cur_dev)) {
23 		printk("Ethernet reference clock gpio port is not ready!\n");
24 		return -ENODEV;
25 	}
26 
27 	gpio_pin_configure(cur_dev, ETH_REF_CLK_GPIO_PIN, GPIO_OUTPUT);
28 	gpio_pin_set(cur_dev, ETH_REF_CLK_GPIO_PIN, 0);
29 
30 	CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
31 
32 	/* enable CMU_CLK2 as RMII reference clock */
33 	CMU->CTRL |= CMU_CTRL_CLKOUTSEL2_HFXO;
34 	CMU->ROUTELOC0 = (CMU->ROUTELOC0 & ~_CMU_ROUTELOC0_CLKOUT2LOC_MASK) |
35 			 (ETH_REF_CLK_LOCATION << _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT);
36 	CMU->ROUTEPEN |= CMU_ROUTEPEN_CLKOUT2PEN;
37 
38 	return 0;
39 }
40 
41 /* needs to be done after GPIO driver init and device tree available */
42 SYS_INIT(efm32gg_slwstk6121a_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
43