1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 5)>,
10				<NRF_PSEL(UART_RX, 0, 11)>;
11		};
12	};
13
14	uart0_sleep: uart0_sleep {
15		group1 {
16			psels = <NRF_PSEL(UART_TX, 0, 5)>,
17				<NRF_PSEL(UART_RX, 0, 11)>;
18			low-power-enable;
19		};
20	};
21
22	i2c0_default: i2c0_default {
23		group1 {
24			psels = <NRF_PSEL(TWIM_SDA, 0, 29)>,
25				<NRF_PSEL(TWIM_SCL, 0, 28)>;
26			bias-pull-up;
27		};
28	};
29
30	i2c0_sleep: i2c0_sleep {
31		group1 {
32			psels = <NRF_PSEL(TWIM_SDA, 0, 29)>,
33				<NRF_PSEL(TWIM_SCL, 0, 28)>;
34			low-power-enable;
35		};
36	};
37
38	spi1_default: spi1_default {
39		group1 {
40			psels = <NRF_PSEL(SPIM_SCK, 0, 4)>,
41				<NRF_PSEL(SPIM_MOSI, 0, 6)>,
42				<NRF_PSEL(SPIM_MISO, 0, 7)>;
43		};
44	};
45
46	spi1_sleep: spi1_sleep {
47		group1 {
48			psels = <NRF_PSEL(SPIM_SCK, 0, 4)>,
49				<NRF_PSEL(SPIM_MOSI, 0, 6)>,
50				<NRF_PSEL(SPIM_MISO, 0, 7)>;
51			low-power-enable;
52		};
53	};
54
55	spi2_default: spi2_default {
56		group1 {
57			psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
58				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
59				<NRF_PSEL(SPIM_MISO, 0, 18)>;
60		};
61	};
62
63	spi2_sleep: spi2_sleep {
64		group1 {
65			psels = <NRF_PSEL(SPIM_SCK, 0, 16)>,
66				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
67				<NRF_PSEL(SPIM_MISO, 0, 18)>;
68			low-power-enable;
69		};
70	};
71
72	pwm0_default: pwm0_default {
73		group1 {
74			psels = <NRF_PSEL(PWM_OUT0, 0, 22)>;
75			nordic,invert;
76		};
77	};
78
79	pwm0_sleep: pwm0_sleep {
80		group1 {
81			psels = <NRF_PSEL(PWM_OUT0, 0, 22)>;
82			low-power-enable;
83		};
84	};
85
86};
87