1/* SPDX-License-Identifier: Apache-2.0 */ 2/* Copyright (c) 2019 Intel Corp. */ 3 4/dts-v1/; 5 6#include <mem.h> 7 8#ifndef DT_DRAM_BASE 9#define DT_DRAM_BASE 0 10#endif 11#ifndef DT_DRAM_SIZE 12#define DT_DRAM_SIZE DT_SIZE_M(32) 13#endif 14#define DT_FLASH_SIZE DT_SIZE_K(4096) 15 16#include <intel/atom.dtsi> 17#include <zephyr/dt-bindings/pcie/pcie.h> 18 19/ { 20 model = "QEMU X86 emulator"; 21 compatible = "qemu,x86_emulator"; 22 23 flash0: flash@500000 { 24 compatible = "soc-nv-flash"; 25 reg = <0x00500000 DT_FLASH_SIZE>; 26 }; 27 28 aliases { 29 uart-0 = &uart0; 30 uart-1 = &uart1; 31 eeprom-0 = &eeprom0; 32 eeprom-1 = &eeprom1; 33 rtc = &rtc; 34 }; 35 36 chosen { 37 zephyr,sram = &dram0; 38 zephyr,flash = &flash0; 39 zephyr,console = &uart0; 40 zephyr,bt-hci = &bt_hci_uart; 41 zephyr,shell-uart = &uart0; 42 zephyr,uart-pipe = &uart1; 43 zephyr,bt-mon-uart = &uart1; 44 zephyr,code-partition = &slot0_partition; 45 zephyr,flash-controller = &sim_flash; 46 zephyr,ieee802154 = &ieee802154; 47 zephyr,canbus = &can0; 48 }; 49 50 pcie0: pcie0 { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 compatible = "pcie-controller"; 54 acpi-hid = "PNP0A08"; 55 ranges; 56 57 can0: can0 { 58 compatible = "kvaser,pcican"; 59 status = "okay"; 60 vendor-id = <0x10e8>; 61 device-id = <0x8406>; 62 interrupts = <11 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 63 interrupt-parent = <&intc>; 64 65 can-transceiver { 66 max-bitrate = <1000000>; 67 }; 68 }; 69 70 eth0: eth0 { 71 compatible = "intel,e1000"; 72 73 vendor-id = <0x8086>; 74 device-id = <0x100e>; 75 76 interrupts = <11 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 77 interrupt-parent = <&intc>; 78 79 status = "okay"; 80 }; 81 }; 82 83 sim_flash: sim_flash { 84 compatible = "zephyr,sim-flash"; 85 86 #address-cells = <1>; 87 #size-cells = <1>; 88 erase-value = <0xff>; 89 90 flash_sim0: flash_sim@0 { 91 compatible = "soc-nv-flash"; 92 reg = <0x00000000 DT_SIZE_K(1024)>; 93 94 erase-block-size = <1024>; 95 write-block-size = <4>; 96 }; 97 }; 98 99 eeprom1: eeprom1 { 100 status = "okay"; 101 compatible = "zephyr,emu-eeprom"; 102 size = <DT_SIZE_K(4)>; 103 pagesize = <DT_SIZE_K(8)>; 104 partition = <&eepromemu_partition>; 105 rambuf; 106 }; 107 108 eeprom0: eeprom0 { 109 status = "okay"; 110 compatible = "zephyr,sim-eeprom"; 111 size = <DT_SIZE_K(4)>; 112 }; 113 114 ieee802154: ieee802154 { 115 compatible = "zephyr,ieee802154-uart-pipe"; 116 }; 117 118}; 119 120&uart0 { 121 status = "okay"; 122 current-speed = <115200>; 123}; 124 125&uart1 { 126 status = "okay"; 127 current-speed = <115200>; 128 129 bt_hci_uart: bt_hci_uart { 130 compatible = "zephyr,bt-hci-uart"; 131 status = "okay"; 132 }; 133}; 134 135&hpet { 136 status = "okay"; 137}; 138 139&flash_sim0 { 140 141 partitions { 142 compatible = "fixed-partitions"; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 146 /* 147 * Storage partition will be used by FCB/LittleFS/NVS 148 * if enabled. 149 */ 150 storage_partition: partition@1000 { 151 label = "storage"; 152 reg = <0x00001000 0x00010000>; 153 }; 154 155 slot0_partition: partition@11000 { 156 label = "image-0"; 157 reg = <0x00011000 0x00010000>; 158 }; 159 slot1_partition: partition@21000 { 160 label = "image-1"; 161 reg = <0x00021000 0x00010000>; 162 }; 163 eepromemu_partition: partition@31000 { 164 label = "eeprom-emu"; 165 reg = <0x00031000 0x00010000>; 166 }; 167 }; 168}; 169 170&cpu { 171 compatible = "intel,x86"; 172}; 173