1/* 2 * Copyright 2023 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "vmu_rt1170-pinctrl.dtsi" 8#include <nxp/nxp_rt1170.dtsi> 9 10/ { 11 aliases { 12 led0 = &green_led; 13 led1 = &red_led; 14 led2 = &blue_led; 15 sdhc0 = &usdhc1; 16 }; 17 18 leds { 19 compatible = "gpio-leds"; 20 green_led: led-1 { 21 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 22 label = "Green LED"; 23 }; 24 25 red_led: led-2 { 26 gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; 27 label = "Red LED"; 28 }; 29 30 blue_led: led-3 { 31 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 32 label = "Blue LED"; 33 }; 34 }; 35}; 36 37&semc { 38 status = "disabled"; 39}; 40 41&lpuart1 { 42 status = "okay"; 43 pinctrl-0 = <&pinmux_lpuart1>; 44 pinctrl-names = "default"; 45 current-speed = <115200>; 46}; 47 48&lpuart3 { 49 status = "okay"; 50 pinctrl-0 = <&pinmux_lpuart3>; 51 pinctrl-names = "default"; 52 current-speed = <115200>; 53}; 54 55&lpuart4 { 56 status = "okay"; 57 pinctrl-0 = <&pinmux_lpuart4>; 58 pinctrl-names = "default"; 59 current-speed = <115200>; 60}; 61 62&lpuart5 { 63 status = "okay"; 64 pinctrl-0 = <&pinmux_lpuart5>; 65 pinctrl-names = "default"; 66 current-speed = <115200>; 67}; 68 69&lpuart6 { 70 status = "okay"; 71 pinctrl-0 = <&pinmux_lpuart6>; 72 pinctrl-names = "default"; 73 current-speed = <115200>; 74}; 75 76&lpuart8 { 77 status = "okay"; 78 pinctrl-0 = <&pinmux_lpuart8>; 79 pinctrl-names = "default"; 80 current-speed = <115200>; 81}; 82 83&lpuart10 { 84 status = "okay"; 85 pinctrl-0 = <&pinmux_lpuart10>; 86 pinctrl-names = "default"; 87 current-speed = <115200>; 88}; 89 90&lpuart11 { 91 status = "okay"; 92 pinctrl-0 = <&pinmux_lpuart11>; 93 pinctrl-names = "default"; 94 current-speed = <115200>; 95}; 96 97&green_led { 98 status = "okay"; 99}; 100 101&enet1g_mac { 102 pinctrl-0 = <&pinmux_enet1g>; 103 pinctrl-names = "default"; 104 phy-handle = <&enet1g_phy>; 105 phy-connection-type = "rmii"; 106 zephyr,random-mac-address; 107}; 108 109&enet1g_mdio { 110 pinctrl-0 = <&pinmux_enet1g_mdio>; 111 pinctrl-names = "default"; 112 enet1g_phy: phy@1 { 113 compatible = "nxp,tja1103"; 114 reg = <1>; 115 master-slave = "master"; 116 }; 117}; 118 119&enet1g_ptp_clock { 120 pinctrl-0 = <&pinmux_enet1g_ptp>; 121 pinctrl-names = "default"; 122}; 123 124&flexcan1 { 125 pinctrl-0 = <&pinmux_flexcan1>; 126 pinctrl-names = "default"; 127}; 128 129&flexcan2 { 130 pinctrl-0 = <&pinmux_flexcan2>; 131 pinctrl-names = "default"; 132}; 133 134&flexcan3 { 135 pinctrl-0 = <&pinmux_flexcan3>; 136 pinctrl-names = "default"; 137}; 138 139&lpi2c1 { 140 pinctrl-0 =<&pinmux_lpi2c1>; 141 pinctrl-names = "default"; 142}; 143 144&lpi2c2 { 145 pinctrl-0 =<&pinmux_lpi2c2>; 146 pinctrl-names = "default"; 147}; 148 149&lpi2c3 { 150 pinctrl-0 =<&pinmux_lpi2c3>; 151 pinctrl-names = "default"; 152}; 153 154&lpi2c6 { 155 pinctrl-0 =<&pinmux_lpi2c6>; 156 pinctrl-names = "default"; 157}; 158 159&lpspi1 { 160 pinctrl-0 = <&pinmux_lpspi1>; 161 pinctrl-names = "default"; 162}; 163 164&lpspi2 { 165 pinctrl-0 = <&pinmux_lpspi2>; 166 pinctrl-names = "default"; 167}; 168 169&lpspi3 { 170 pinctrl-0 = <&pinmux_lpspi3>; 171 pinctrl-names = "default"; 172}; 173 174&lpspi6 { 175 pinctrl-0 = <&pinmux_lpspi6>; 176 pinctrl-names = "default"; 177}; 178 179&lpadc1 { 180 pinctrl-0 = <&pinmux_lpadc1>; 181 pinctrl-names = "default"; 182}; 183 184&flexspi { 185 pinctrl-0 = <&pinmux_flexspi1>; 186 pinctrl-names = "default"; 187}; 188 189&usdhc1 { 190 pinctrl-0 = <&pinmux_usdhc1>; 191 pinctrl-names = "default"; 192}; 193 194&flexspi { 195 status = "okay"; 196 ahb-prefetch; 197 ahb-read-addr-opt; 198 rx-clock-source = <1>; 199 reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; 200 mx25um51345g: mx25um51345g@0 { 201 compatible = "nxp,imx-flexspi-mx25um51345g"; 202 /* MX25UM51245G is 64MB, 512MBit flash part */ 203 size = <DT_SIZE_M(64 * 8)>; 204 reg = <0>; 205 spi-max-frequency = <200000000>; 206 status = "okay"; 207 jedec-id = [c2 81 3a]; 208 erase-block-size = <4096>; 209 write-block-size = <2>; /* FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR set */ 210 211 partitions { 212 compatible = "fixed-partitions"; 213 #address-cells = <1>; 214 #size-cells = <1>; 215 boot_partition: partition@0 { 216 label = "mcuboot"; 217 reg = <0x00000000 DT_SIZE_K(128)>; 218 }; 219 /* The MCUBoot swap-move algorithm uses the last 3 sectors 220 * of the primary slot0 for swap status and move. 221 */ 222 slot0_partition: partition@20000 { 223 label = "image-0"; 224 reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(3 * 4))>; 225 }; 226 slot1_partition: partition@32E000 { 227 label = "image-1"; 228 reg = <0x0032E000 DT_SIZE_M(3)>; 229 }; 230 storage_partition: partition@62E000 { 231 label = "storage"; 232 reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(140))>; 233 }; 234 }; 235 }; 236}; 237