1# Copyright 2022,2024 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4if BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1
5
6config BUILD_OUTPUT_BIN
7	default n
8
9if SERIAL
10
11config UART_INTERRUPT_DRIVEN
12	default y
13
14config UART_CONSOLE
15	default y
16
17endif # SERIAL
18
19if SHELL
20
21config SHELL_STACK_SIZE
22	default 4096
23
24endif # SHELL
25
26if NETWORKING
27
28config NET_L2_ETHERNET
29	default y  if !NET_LOOPBACK && !NET_TEST
30
31endif # NETWORKING
32
33if XIP
34# Offset between CRAM AXIM and CRAM AXIF, code will be downloaded
35# over AXIM interface
36config BUILD_OUTPUT_ADJUST_LMA
37	default "-0x47800000"
38
39config CPU_CORTEX_R52_CACHE_SEGREGATION
40	default y
41
42config CPU_CORTEX_R52_ICACHE_FLASH_WAY
43	default 4
44
45config CPU_CORTEX_R52_DCACHE_FLASH_WAY
46	default 1
47endif # XIP
48
49endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1
50