1/*
2 * NOTE: File generated by gen_board_pinctrl.py
3 * from MIMXRT685-EVK.mex
4 *
5 * Copyright 2022, 2024 NXP
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9
10#include <nxp/nxp_imx/rt/MIMXRT685SFVKB-pinctrl.h>
11
12&pinctrl {
13	pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
14		group0 {
15			pinmux = <FC0_RXD_SDA_MOSI_DATA_PIO0_2>;
16			input-enable;
17			slew-rate = "normal";
18			drive-strength = "normal";
19		};
20		group1 {
21			pinmux = <FC0_TXD_SCL_MISO_WS_PIO0_1>;
22			slew-rate = "normal";
23			drive-strength = "normal";
24		};
25	};
26
27	pinmux_flexcomm1_i2s: pinmux_flexcomm1_i2s {
28		group0 {
29			pinmux = <FC1_RXD_SDA_MOSI_DATA_PIO0_9>;
30			input-enable;
31			slew-rate = "normal";
32			drive-strength = "high";
33		};
34	};
35
36	pinmux_flexcomm2_i2c: pinmux_flexcomm2_i2c {
37		group0 {
38			pinmux = <FC2_CTS_SDA_SSEL0_PIO0_17>,
39				<FC2_RTS_SCL_SSEL1_PIO0_18>;
40			bias-pull-up;
41			input-enable;
42			slew-rate = "normal";
43			drive-strength = "high";
44			drive-open-drain;
45		};
46	};
47
48	pinmux_flexcomm3_i2s: pinmux_flexcomm3_i2s {
49		group0 {
50			pinmux = <FC3_RXD_SDA_MOSI_DATA_PIO0_23>,
51				<FC3_TXD_SCL_MISO_WS_PIO0_22>,
52				<FC3_SCK_PIO0_21>,
53				<MCLK_PIO1_10>;
54			input-enable;
55			slew-rate = "normal";
56			drive-strength = "high";
57		};
58	};
59
60	pinmux_flexcomm4_usart: pinmux_flexcomm4_usart {
61		group0 {
62			pinmux = <FC4_RXD_SDA_MOSI_DATA_PIO0_30>;
63			input-enable;
64			slew-rate = "normal";
65			drive-strength = "normal";
66		};
67		group1 {
68			pinmux = <FC4_TXD_SCL_MISO_WS_PIO0_29>;
69			slew-rate = "normal";
70			drive-strength = "normal";
71		};
72	};
73
74	pinmux_flexcomm5_spi: pinmux_flexcomm5_spi {
75		group0 {
76			pinmux = <FC5_SCK_PIO1_3>,
77				<FC5_TXD_SCL_MISO_WS_PIO1_4>,
78				<FC5_RXD_SDA_MOSI_DATA_PIO1_5>,
79				<FC5_CTS_SDA_SSEL0_PIO1_6>;
80			input-enable;
81			slew-rate = "normal";
82			drive-strength = "normal";
83		};
84	};
85
86	pinmux_dmic0: pinmux_dmic0 {
87		group0 {
88			pinmux = <DMIC0_DATA2_3_PIO2_21>, <DMIC0_DATA0_1_PIO2_20>,
89			       <DMIC0_CLK0_1_PIO2_16>;
90			slew-rate = "normal";
91			drive-strength = "normal";
92			input-enable;
93		};
94	};
95
96	pinmux_flexspi: pinmux_flexspi {
97		group0 {
98			pinmux = <FLEXSPI0B_DATA0_PIO1_11>,
99				<FLEXSPI0B_DATA1_PIO1_12>,
100				<FLEXSPI0B_DATA2_PIO1_13>,
101				<FLEXSPI0B_DATA3_PIO1_14>,
102				<FLEXSPI0B_SCLK_PIO1_29>,
103				<FLEXSPI0B_DATA4_PIO2_17>,
104				<FLEXSPI0B_DATA5_PIO2_18>,
105				<FLEXSPI0B_SS0_N_PIO2_19>,
106				<FLEXSPI0B_DATA6_PIO2_22>,
107				<FLEXSPI0B_DATA7_PIO2_23>;
108			input-enable;
109			slew-rate = "normal";
110			drive-strength = "high";
111		};
112		group1 {
113			pinmux = <GPIO_PIO212_PIO2_12>;
114			slew-rate = "normal";
115			drive-strength = "normal";
116		};
117	};
118	/*
119	 * The current test and sample applications uses a single channel for
120	 * testing so we only need to enable the pin for that single use.
121	 *
122	 * If your application requires more then the mappings are as follows
123	 * for the rt685_evk:
124	 *
125	 * +---------+------+---------+-------+
126	 * |  Port#  | ADC  |Schematic|Arduino|
127	 * |   pin   | Chn# |         |header |
128	 * +---------+------+---------+-------+
129	 * | PIO0_5  | CH0A | ADC0_0  | J30.1 |
130	 * +---------+------+---------+-------+
131	 * | PIO0_6  | CH0B | ADC0_8  | J30.2 |
132	 * +---------+------+---------+-------+
133	 * | PIO0_12 | CH1A | ADC0_1  |       |
134	 * +---------+------+---------+-------+
135	 * | PIO0_13 | CH1B | ADC0_9  |       |
136	 * +---------+------+---------+-------+
137	 * | PIO0_19 | CH2A | ADC0_2  | J30.3 |
138	 * +---------+------+---------+-------+
139	 * | PIO0_20 | CH2B | ADC0_10 | J30.4 |
140	 * +---------+------+---------+-------+
141	 * | PIO0_26 | CH3A | ADC0_3  |       |
142	 * +---------+------+---------+-------+
143	 * | PIO0_27 | CH3B | ADC0_11 |       |
144	 * +---------+------+---------+-------+
145	 * | PIO1_8  | CH4A | ADC0_4  |       |
146	 * +---------+------+---------+-------+
147	 * | PIO1_9  | CH4B | ADC0_12 |       |
148	 * +---------+------+---------+-------+
149	 * | PIO3_23 | CH5A | ADC0_5  |       |
150	 * +---------+------+---------+-------+
151	 * | PIO3_24 | CH5B | ADC0_13 |       |
152	 * +---------+------+---------+-------+
153	 *
154	 * Per the mimxrt6xx reference manual, The channels 0-5 are analong input.
155	 * Optionally, channels 0A through 5A can be paired with channels 0B
156	 * through 5B for differential input on their respective ADC channel.
157	 *
158	 */
159	pinmux_lpadc0: pinmux_lpadc0 {
160		group0 {
161			pinmux = <ADC0_CH0_PIO0_5>,
162				<ADC0_CH8_PIO0_6>;
163			slew-rate = "normal";
164			drive-strength = "normal";
165			nxp,analog-mode;
166		};
167	};
168
169	pinmux_pmic_i2c: pinmux_pmic_i2c {
170		group0 {
171			pinmux = <PMIC_I2C_SCL>,
172				<PMIC_I2C_SDA>;
173			bias-pull-up;
174			input-enable;
175			slew-rate = "normal";
176			drive-strength = "normal";
177			drive-open-drain;
178		};
179	};
180
181	pinmux_sctimer: pinmux_sctimer {
182		group0 {
183			pinmux = <SCT0_OUT7_PIO0_27>,
184				<SCT0_OUT0_PIO0_14>,
185				<SCT0_OUT6_PIO0_26>,
186				<SCT0_OUT6_PIO0_31>;
187			slew-rate = "normal";
188			drive-strength = "normal";
189		};
190	};
191
192	pinmux_usdhc: pinmux_usdhc {
193		group0 {
194			pinmux = <SD0_CMD_PIO1_31>,
195				<USDHC0_USDHC_DATA0_PIO2_0>,
196				<USDHC0_USDHC_DATA1_PIO2_1>,
197				<USDHC0_USDHC_DATA2_PIO2_2>,
198				<USDHC0_USDHC_DATA3_PIO2_3>,
199				<GPIO_PIO29_PIO2_9>;
200			bias-pull-up;
201			input-enable;
202			slew-rate = "normal";
203			drive-strength = "normal";
204		};
205		group1 {
206			pinmux = <SD0_CLK_PIO1_30>;
207			input-enable;
208			slew-rate = "normal";
209			drive-strength = "normal";
210		};
211		group2 {
212			pinmux = <GPIO_PIO210_PIO2_10>,
213				<GPIO_PIO24_PIO2_4>;
214			slew-rate = "normal";
215			drive-strength = "normal";
216		};
217	};
218
219	pinmux_i3c: pinmux_i3c {
220		group0 {
221			pinmux = <I3C0_SCL_PIO2_29>,
222				<I3C0_SDA_PIO2_30>;
223			input-enable;
224			slew-rate = "slow";
225			drive-strength = "high";
226		};
227
228		group1 {
229			pinmux = <I3C0_PUR_PIO2_31>;
230			slew-rate = "normal";
231			drive-strength = "normal";
232		};
233	};
234
235	pinmux_ctimer2_pwm: pinmux_ctimer2_pwm {
236		group0 {
237			pinmux = <CTIMER2_MATCH0_PIO0_14>;
238			slew-rate = "normal";
239			drive-strength = "normal";
240		};
241	};
242
243};
244