1/*
2 * Copyright 2021,2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include "mimxrt1170_evk-pinctrl.dtsi"
8#include <nxp/nxp_rt1170.dtsi>
9#include <zephyr/dt-bindings/input/input-event-codes.h>
10
11/ {
12	aliases {
13		led0 = &green_led;
14		led1 = &red_led;
15		sw0 = &user_button;
16		magn0 = &fxos8700;
17		accel0 = &fxos8700;
18		sdhc0 = &usdhc1;
19		pwm-led0 = &green_pwm_led;
20		mcuboot-button0 = &user_button;
21	};
22
23	leds {
24		compatible = "gpio-leds";
25		green_led: led-1 {
26			gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
27			label = "User LED D6";
28		};
29
30		red_led: led-2 {
31			gpios = <&gpio9 25 GPIO_ACTIVE_LOW>;
32			label = "User LED D34";
33		};
34	};
35
36	gpio_keys {
37		compatible = "gpio-keys";
38		user_button: button-1 {
39			label = "User SW7";
40			gpios = <&gpio13 0 GPIO_ACTIVE_HIGH>;
41			zephyr,code = <INPUT_KEY_0>;
42		};
43	};
44
45	pwmleds {
46		compatible = "pwm-leds";
47
48		green_pwm_led: green_pwm_led {
49			pwms = <&flexpwm1_pwm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
50		};
51	};
52};
53
54&lpi2c5 {
55	status = "okay";
56	pinctrl-0 = <&pinmux_lpi2c5>;
57	pinctrl-names = "default";
58
59	fxos8700: fxos8700@1f {
60		compatible = "nxp,fxos8700";
61		reg = <0x1f>;
62
63		/* Two zero ohm resistors (R256 and R270) isolate sensor
64		 * interrupt gpios from the soc and are unpopulated by default.
65		 * Note that if you populate them, they conflict with camera and
66		 * ethernet PHY reset signals.
67		 */
68		int1-gpios = <&gpio11 14 GPIO_ACTIVE_LOW>;
69		int2-gpios = <&gpio11 15 GPIO_ACTIVE_LOW>;
70	};
71};
72
73&lpuart1 {
74	status = "okay";
75	pinctrl-0 = <&pinmux_lpuart1>;
76	pinctrl-1 = <&pinmux_lpuart1_sleep>;
77	pinctrl-names = "default", "sleep";
78	current-speed = <115200>;
79};
80
81&lpuart2 {
82	pinctrl-0 = <&pinmux_lpuart2>;
83	pinctrl-1 = <&pinmux_lpuart2_sleep>;
84	pinctrl-names = "default", "sleep";
85};
86
87&user_button {
88	status = "okay";
89};
90
91&green_led {
92	status = "okay";
93};
94
95&flexpwm1_pwm2 {
96	status = "okay";
97	pinctrl-0 = <&pinmux_flexpwm1>;
98	pinctrl-names = "default";
99};
100
101&enet_mac {
102	status = "okay";
103	pinctrl-0 = <&pinmux_enet>;
104	pinctrl-names = "default";
105	phy-handle = <&phy>;
106	phy-connection-type = "rmii";
107	zephyr,random-mac-address;
108};
109
110&enet_mdio {
111	status = "okay";
112	pinctrl-0 = <&pinmux_enet_mdio>;
113	pinctrl-names = "default";
114	phy: phy@0 {
115		compatible = "microchip,ksz8081";
116		reg = <0>;
117		status = "okay";
118		reset-gpios = <&gpio12 12 GPIO_ACTIVE_HIGH>;
119		int-gpios = <&gpio9 11 GPIO_ACTIVE_HIGH>;
120		microchip,interface-type = "rmii";
121	};
122};
123
124&enet_ptp_clock {
125	status = "okay";
126	pinctrl-0 = <&pinmux_ptp>;
127	pinctrl-names = "default";
128};
129
130&enet1g_mac {
131	status = "disabled";
132	pinctrl-0 = <&pinmux_enet1g>;
133	pinctrl-names = "default";
134	phy-handle = <&enet1g_phy>;
135	phy-connection-type = "rgmii";
136	zephyr,random-mac-address;
137};
138
139&enet1g_mdio {
140	status = "disabled";
141	pinctrl-0 = <&pinmux_enet1g_mdio>;
142	pinctrl-names = "default";
143	enet1g_phy: phy@1 {
144		compatible = "realtek,rtl8211f";
145		reg = <1>;
146		status = "disabled";
147		reset-gpios = <&gpio11 14 GPIO_ACTIVE_HIGH>;
148		int-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
149	};
150};
151
152&enet1g_ptp_clock {
153	status = "disabled";
154	pinctrl-0 = <&pinmux_enet1g_ptp>;
155	pinctrl-names = "default";
156};
157
158&csi {
159	pinctrl-0 = <&pinmux_csi>;
160	pinctrl-names = "default";
161};
162
163&lpi2c6 {
164	pinctrl-0 = <&pinmux_lpi2c6>;
165	pinctrl-names = "default";
166};
167
168&flexcan3 {
169	pinctrl-0 = <&pinmux_flexcan3>;
170	pinctrl-names = "default";
171};
172
173&lcdif {
174	pinctrl-0 = <&pinmux_lcdif>;
175	pinctrl-names = "default";
176};
177
178&lpi2c1 {
179	pinctrl-0 =<&pinmux_lpi2c1>;
180	pinctrl-names = "default";
181};
182
183&lpspi1 {
184	pinctrl-0 = <&pinmux_lpspi1>;
185	pinctrl-names = "default";
186};
187
188&lpuart2 {
189	pinctrl-0 = <&pinmux_lpuart2>;
190	pinctrl-1 = <&pinmux_lpuart2_sleep>;
191	pinctrl-names = "default", "sleep";
192};
193
194&sai1 {
195	pinctrl-0 = <&pinmux_sai1>;
196	pinctrl-names = "default";
197};
198
199&lpadc0 {
200	pinctrl-0 = <&pinmux_lpadc0>;
201	pinctrl-names = "default";
202};
203
204&flexspi {
205	pinctrl-0 = <&pinmux_flexspi1>;
206	pinctrl-names = "default";
207};
208
209&usdhc1 {
210	pinctrl-0 = <&pinmux_usdhc1>;
211	pinctrl-1 = <&pinmux_usdhc1_dat3_nopull>;
212	pinctrl-names = "default", "nopull";
213};
214
215&flexspi {
216	status = "okay";
217	ahb-prefetch;
218	ahb-read-addr-opt;
219	rx-clock-source = <1>;
220	reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
221	is25wp128: is25wp128@0 {
222		compatible = "nxp,imx-flexspi-nor";
223		size = <DT_SIZE_M(16*8)>;
224		reg = <0>;
225		spi-max-frequency = <104000000>;
226		status = "okay";
227		jedec-id = [9d 70 17];
228		erase-block-size = <4096>;
229		write-block-size = <1>;
230
231		partitions {
232			compatible = "fixed-partitions";
233			#address-cells = <1>;
234			#size-cells = <1>;
235
236			boot_partition: partition@0 {
237				label = "mcuboot";
238				reg = <0x00000000 DT_SIZE_K(128)>;
239			};
240			/* The MCUBoot swap-move algorithm uses the last 3 sectors
241			 * of the primary slot0 for swap status and move.
242			 */
243			slot0_partition: partition@20000 {
244				label = "image-0";
245				reg = <0x00020000 (DT_SIZE_M(7) + DT_SIZE_K(12))>;
246			};
247			slot1_partition: partition@723000 {
248				label = "image-1";
249				reg = <0x00723000 DT_SIZE_M(7)>;
250			};
251			storage_partition: partition@E23000 {
252				label = "storage";
253				reg = <0x00E23000 (DT_SIZE_M(2) - DT_SIZE_K(140))>;
254			};
255		};
256	};
257};
258
259&pxp {
260	status = "okay";
261};
262