1/*
2 * Copyright 2022,2024 NXP
3 * SPDX-License-Identifier: Apache-2.0
4 *
5 */
6
7#include <nxp/nxp_imx/mimx8mm6dvtlz-pinctrl.dtsi>
8
9&pinctrl {
10	uart2_default: uart2_default {
11		group0 {
12			pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx>,
13				<&iomuxc_uart2_txd_uart_tx_uart2_tx>;
14			slew-rate = "fast";
15			drive-strength = "x6";
16		};
17	};
18
19	uart4_default: uart4_default {
20		group0 {
21			pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
22				<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
23			slew-rate = "fast";
24			drive-strength = "x6";
25		};
26	};
27
28	pinmux_enet: pinmux_enet {
29		group0 {
30			pinmux = <&iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0>,
31				<&iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1>,
32				<&iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2>,
33				<&iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3>,
34				<&iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc>,
35				<&iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
36			slew-rate = "fast";
37			drive-strength = "x6";
38		};
39
40		group1 {
41			pinmux = <&iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
42				<&iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
43				<&iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
44				<&iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
45				<&iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
46				<&iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>;
47			slew-rate = "fast";
48			drive-strength = "x1";
49		};
50
51		group2 {
52			pinmux = <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>;
53			slew-rate = "fast";
54			drive-strength = "x1";
55		};
56	};
57
58	pinmux_mdio: pinmux_mdio {
59		group0 {
60			pinmux = <&iomuxc_enet_mdc_enet_mdc_enet1_mdc>,
61				<&iomuxc_enet_mdio_enet_mdio_enet1_mdio>;
62			slew-rate = "slow";
63			drive-strength = "x6";
64		};
65	};
66};
67