1/*
2 * Copyright 2024 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8#include <nxp/kinetis/MKE17Z512VLL9-pinctrl.h>
9
10&pinctrl {
11	adc0_default: adc0_default {
12		group0 {
13			pinmux = <ADC0_SE0_PTE9>;
14			drive-strength = "low";
15			slew-rate = "slow";
16		};
17	};
18
19	/* Configures pin routing and optionally pin electrical features. */
20	lpuart2_default: lpuart2_default {
21		group0 {
22			pinmux = <LPUART2_TX_PTE12>,
23					<LPUART2_RX_PTD17>;
24			drive-strength = "low";
25			slew-rate = "slow";
26		};
27	};
28
29	ftm2_default: ftm2_default {
30		group0 {
31			pinmux = <FTM2_CH0_PTD10>,
32				<FTM2_CH2_PTD12>,
33				<FTM2_CH3_PTD5>;
34			drive-strength = "low";
35			slew-rate = "slow";
36		};
37	};
38
39	lpi2c0_default: lpi2c0_default {
40		group0 {
41			pinmux = <LPI2C0_SDA_PTA2>,
42				<LPI2C0_SCL_PTA3>;
43			bias-pull-up;
44			drive-strength = "low";
45			slew-rate = "slow";
46		};
47	};
48
49	lpi2c1_default: lpi2c1_default {
50		group0 {
51			pinmux = <LPI2C1_SDA_PTE0>,
52				<LPI2C1_SCL_PTE1>;
53			bias-pull-up;
54			drive-strength = "low";
55			slew-rate = "slow";
56		};
57	};
58
59	uart1_default: uart1_default {
60		group0 {
61			pinmux = <SCI1_RX_PTC16>,
62				<SCI1_TX_PTC17>;
63			drive-strength = "low";
64			slew-rate = "slow";
65		};
66	};
67
68	lpspi0_default: lpspi0_default {
69		group0 {
70			pinmux = <LPSPI0_SCK_PTE0>,
71				<LPSPI0_SIN_PTE1>,
72				<LPSPI0_SOUT_PTE2>,
73				<LPSPI0_PCS2_PTE6>;
74			bias-pull-up;
75			drive-strength = "low";
76			slew-rate = "slow";
77		};
78	};
79
80	flexio_pwm_default: flexio_pwm_default {
81		group0 {
82			pinmux = <FXIO_D3_PTD5>,
83				<FXIO_D5_PTD3>;
84			drive-strength = "low";
85			slew-rate = "slow";
86		};
87	};
88};
89