1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 6)>,
10				<NRF_PSEL(UART_RTS, 0, 5)>;
11		};
12		group2 {
13			psels = <NRF_PSEL(UART_RX, 0, 8)>,
14				<NRF_PSEL(UART_CTS, 0, 7)>;
15			bias-pull-up;
16		};
17	};
18
19	uart0_sleep: uart0_sleep {
20		group1 {
21			psels = <NRF_PSEL(UART_TX, 0, 6)>,
22				<NRF_PSEL(UART_RX, 0, 8)>,
23				<NRF_PSEL(UART_RTS, 0, 5)>,
24				<NRF_PSEL(UART_CTS, 0, 7)>;
25			low-power-enable;
26		};
27	};
28
29	uart1_default: uart1_default {
30		group1 {
31			psels = <NRF_PSEL(UART_RX, 1, 1)>;
32			bias-pull-up;
33		};
34		group2 {
35			psels = <NRF_PSEL(UART_TX, 1, 2)>;
36		};
37	};
38
39	uart1_sleep: uart1_sleep {
40		group1 {
41			psels = <NRF_PSEL(UART_RX, 1, 1)>,
42				<NRF_PSEL(UART_TX, 1, 2)>;
43			low-power-enable;
44		};
45	};
46
47	i2c0_default: i2c0_default {
48		group1 {
49			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
50				<NRF_PSEL(TWIM_SCL, 0, 27)>;
51		};
52	};
53
54	i2c0_sleep: i2c0_sleep {
55		group1 {
56			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
57				<NRF_PSEL(TWIM_SCL, 0, 27)>;
58			low-power-enable;
59		};
60	};
61
62	i2c1_default: i2c1_default {
63		group1 {
64			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
65				<NRF_PSEL(TWIM_SCL, 0, 31)>;
66		};
67	};
68
69	i2c1_sleep: i2c1_sleep {
70		group1 {
71			psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
72				<NRF_PSEL(TWIM_SCL, 0, 31)>;
73			low-power-enable;
74		};
75	};
76
77	pwm0_default: pwm0_default {
78		group1 {
79			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
80			nordic,invert;
81		};
82	};
83
84	pwm0_sleep: pwm0_sleep {
85		group1 {
86			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
87			low-power-enable;
88		};
89	};
90
91	spi0_default: spi0_default {
92		group1 {
93			psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
94				<NRF_PSEL(SPIM_MOSI, 0, 26)>,
95				<NRF_PSEL(SPIM_MISO, 0, 29)>;
96		};
97	};
98
99	spi0_sleep: spi0_sleep {
100		group1 {
101			psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
102				<NRF_PSEL(SPIM_MOSI, 0, 26)>,
103				<NRF_PSEL(SPIM_MISO, 0, 29)>;
104			low-power-enable;
105		};
106	};
107
108	spi1_default: spi1_default {
109		group1 {
110			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
111				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
112				<NRF_PSEL(SPIM_MISO, 1, 8)>;
113		};
114	};
115
116	spi1_sleep: spi1_sleep {
117		group1 {
118			psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
119				<NRF_PSEL(SPIM_MOSI, 0, 30)>,
120				<NRF_PSEL(SPIM_MISO, 1, 8)>;
121			low-power-enable;
122		};
123	};
124
125	spi2_default: spi2_default {
126		group1 {
127			psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
128				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
129				<NRF_PSEL(SPIM_MISO, 0, 21)>;
130		};
131	};
132
133	spi2_sleep: spi2_sleep {
134		group1 {
135			psels = <NRF_PSEL(SPIM_SCK, 0, 19)>,
136				<NRF_PSEL(SPIM_MOSI, 0, 20)>,
137				<NRF_PSEL(SPIM_MISO, 0, 21)>;
138			low-power-enable;
139		};
140	};
141
142	qspi_default: qspi_default {
143		group1 {
144			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
145				<NRF_PSEL(QSPI_IO0, 0, 20)>,
146				<NRF_PSEL(QSPI_IO1, 0, 21)>,
147				<NRF_PSEL(QSPI_IO2, 0, 22)>,
148				<NRF_PSEL(QSPI_IO3, 0, 23)>,
149				<NRF_PSEL(QSPI_CSN, 0, 17)>;
150			nordic,drive-mode = <NRF_DRIVE_H0H1>;
151		};
152	};
153
154	qspi_sleep: qspi_sleep {
155		group1 {
156			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
157				<NRF_PSEL(QSPI_IO0, 0, 20)>,
158				<NRF_PSEL(QSPI_IO1, 0, 21)>,
159				<NRF_PSEL(QSPI_IO2, 0, 22)>,
160				<NRF_PSEL(QSPI_IO3, 0, 23)>;
161			low-power-enable;
162		};
163		group2 {
164			psels = <NRF_PSEL(QSPI_CSN, 0, 17)>;
165			low-power-enable;
166			bias-pull-up;
167		};
168	};
169
170	spi3_default: spi3_default {
171		group1 {
172			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
173				<NRF_PSEL(SPIM_MISO, 1, 14)>,
174				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
175		};
176	};
177
178	spi3_sleep: spi3_sleep {
179		group1 {
180			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
181				<NRF_PSEL(SPIM_MISO, 1, 14)>,
182				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
183			low-power-enable;
184		};
185	};
186
187};
188