1.. _nrf5340bsim:
2
3NRF5340 simulated boards (BabbleSim)
4####################################
5
6.. contents::
7   :depth: 1
8   :backlinks: entry
9   :local:
10
11
12Overview
13********
14
15To allow simulating nrf5340 SOCs two Zephyr target boards are provided: the
16``nrf5340bsim/nrf5340/cpuapp`` and ``nrf5340bsim/nrf5340/cpunet``.
17
18These use `BabbleSim`_ to simulate the radio activity, and the
19:ref:`POSIX architecture<Posix arch>` and the `native simulator`_ to
20run applications natively on the development system. This has the benefit of
21providing native code execution performance and easy debugging using
22native tools, but inherits :ref:`its limitations <posix_arch_limitations>`.
23
24Just like for the nrf5340dk targets,
25the nrf5340bsim/nrf5340/cpuapp build target provides support for the application core,
26and the nrf5340bsim/nrf5340/cpunet build target provides support for the network
27core on the simulated nRF5340 SOC.
28
29These boards include models of some of the nRF5340 SOC peripherals:
30
31* AAR (Accelerated Address Resolver)
32* AES CCM & AES ECB encryption HW
33* CLOCK (Clock control)
34* DPPI (Distributed Programmable Peripheral Interconnect)
35* EGU (Event Generator Unit)
36* FICR (Factory Information Configuration Registers)
37* GPIO & GPIOTE
38* IPC (Interprocessor communication)
39* MUTEX (Mutual exclusive peripheral)
40* NVMC (Non-Volatile Memory Controller / Flash)
41* RADIO
42* RNG (Random Number Generator)
43* RTC (Real Time Counter)
44* TEMP (Temperature sensor)
45* TIMER
46* UARTE (UART with Easy DMA)
47* UICR (User Information Configuration Registers)
48
49and will use the same drivers as the nrf5340dk targets for these.
50For more information on what is modelled to which level of detail,
51check the `HW models implementation status`_.
52
53Note that unlike a real nrf5340 device, the nrf5340bsim boards have unlimited RAM and flash for
54code.
55
56.. _BabbleSim:
57   https://BabbleSim.github.io
58
59.. _native simulator:
60   https://github.com/BabbleSim/native_simulator/blob/main/docs/README.md
61
62.. _HW models implementation status:
63   https://github.com/BabbleSim/ext_nRF_hw_models/blob/main/docs/README_impl_status.md
64
65
66Building for, and using these boards
67************************************
68
69If you are interested in developing on only one of the MCUs in this SOC, you
70can use the corresponding simulated target, nrf5340bsim/nrf5340/cpuapp or nrf5340bsim/nrf5340/cpunet
71following the instructions from the :ref:`nrf52_bsim board <nrf52bsim_build_and_run>`.
72Simply change the board/target appropriately when building.
73
74
75.. note::
76
77   Unlike in real HW, the net core MCU is set-up to automatically boot at start, to facilitate
78   developing without an image in the application core. You can control
79   this with either :kconfig:option:`CONFIG_NATIVE_SIMULATOR_AUTOSTART_MCU`, or the command line
80   option ``--cpu1_autostart``.
81
82   If an MCU is booted without any image, it will automatically set itself to sleep.
83
84.. _nrf5340bsim_multi_mcu_build:
85
86Assembling both MCUs images into a single executable
87****************************************************
88
89By default, when you build targeting either nrf5340bsim/nrf5340/cpuapp or
90nrf5340bsim/nrf5340/cpunet you will end up with a library (``zephyr/zephyr.elf``) that corresponds
91to that MCU code image, and an executable (``zephyr/zephyr.exe``) that includes the native simulator
92runner, SOC HW models, that image, and an empty image for the other MCU.
93
94If you want to assemble an executable including a previously built image for the other MCU,
95built with either Zephyr's build system or another native simulator compatible build system,
96you can provide that image to the Zephyr build of the second image using
97:kconfig:option:`CONFIG_NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS`.
98
99You can also use :ref:`System build (sysbuild) <sysbuild>` to build your dual MCU executable.
100The best way to understand how, may be to look into how this is done in one of the examples
101in the tree. For example, for :ref:`the nrf53_sync_rtc sample <nrf53_sync_rtc_sample_build_bsim>`,
102:zephyr_file:`samples/boards/nordic/nrf53_sync_rtc/sysbuild.cmake`.
103
104
105.. note::
106
107   These libraries/images are **not** embedded images. You cannot use them for embedded devices,
108   and cannot use an embedded image to assemble a native executable.
109
110TrustZone, TF-M and other security considerations
111*************************************************
112
113ARM's TrustZone is not modelled in these boards. This means that:
114
115* There is no differentiation between secure and non secure execution states or bus accesses.
116* All RAM, flash and peripherals are in principle accessible from all SW. Peripherals with their
117  own interconnect master ports can, in principle, access any other peripheral or RAM area.
118* There is no nrf5340bsim/nrf5340/cpuapp/ns board/build target, or posibility of mixing secure
119  and non-secure images.
120* Currently there is no model of the SPU, and therefore neither flash, RAM areas or peripherals
121  can be labelled as restricted for secure or non secure access.
122* TF-M cannot be used.
123
124Note that the ARM cryptocell-312 peripheral is not modelled. The mbedTLS library can still be used
125but with a SW crypto backend instead of the cryptocell HW acceleration.
126