1/* 2 * Copyright (c) 2022 Nordic Semiconductor 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6&pinctrl { 7 uart0_default: uart0_default { 8 group1 { 9 psels = <NRF_PSEL(UART_TX, 0, 20)>, 10 <NRF_PSEL(UART_RX, 0, 19)>, 11 <NRF_PSEL(UART_RTS, 0, 5)>, 12 <NRF_PSEL(UART_CTS, 0, 7)>; 13 }; 14 }; 15 16 uart0_sleep: uart0_sleep { 17 group1 { 18 psels = <NRF_PSEL(UART_TX, 0, 20)>, 19 <NRF_PSEL(UART_RX, 0, 19)>, 20 <NRF_PSEL(UART_RTS, 0, 5)>, 21 <NRF_PSEL(UART_CTS, 0, 7)>; 22 low-power-enable; 23 }; 24 }; 25 26 i2c0_default: i2c0_default { 27 group1 { 28 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>, 29 <NRF_PSEL(TWIM_SCL, 0, 27)>; 30 }; 31 }; 32 33 i2c0_sleep: i2c0_sleep { 34 group1 { 35 psels = <NRF_PSEL(TWIM_SDA, 0, 26)>, 36 <NRF_PSEL(TWIM_SCL, 0, 27)>; 37 low-power-enable; 38 }; 39 }; 40 41 i2c1_default: i2c1_default { 42 group1 { 43 psels = <NRF_PSEL(TWIM_SDA, 0, 30)>, 44 <NRF_PSEL(TWIM_SCL, 0, 31)>; 45 }; 46 }; 47 48 i2c1_sleep: i2c1_sleep { 49 group1 { 50 psels = <NRF_PSEL(TWIM_SDA, 0, 30)>, 51 <NRF_PSEL(TWIM_SCL, 0, 31)>; 52 low-power-enable; 53 }; 54 }; 55 56 pwm0_default: pwm0_default { 57 group1 { 58 psels = <NRF_PSEL(PWM_OUT0, 0, 22)>, 59 <NRF_PSEL(PWM_OUT1, 0, 23)>, 60 <NRF_PSEL(PWM_OUT2, 0, 24)>; 61 nordic,invert; 62 }; 63 }; 64 65 pwm0_sleep: pwm0_sleep { 66 group1 { 67 psels = <NRF_PSEL(PWM_OUT0, 0, 22)>, 68 <NRF_PSEL(PWM_OUT1, 0, 23)>, 69 <NRF_PSEL(PWM_OUT2, 0, 24)>; 70 low-power-enable; 71 }; 72 }; 73 74 qspi_default: qspi_default { 75 group1 { 76 psels = <NRF_PSEL(QSPI_SCK, 1, 3)>, 77 <NRF_PSEL(QSPI_IO0, 1, 5)>, 78 <NRF_PSEL(QSPI_IO1, 1, 4)>, 79 <NRF_PSEL(QSPI_IO2, 1, 2)>, 80 <NRF_PSEL(QSPI_IO3, 1, 1)>, 81 <NRF_PSEL(QSPI_CSN, 1, 6)>; 82 }; 83 }; 84 85 qspi_sleep: qspi_sleep { 86 group1 { 87 psels = <NRF_PSEL(QSPI_SCK, 1, 3)>, 88 <NRF_PSEL(QSPI_IO0, 1, 5)>, 89 <NRF_PSEL(QSPI_IO1, 1, 4)>, 90 <NRF_PSEL(QSPI_IO2, 1, 2)>, 91 <NRF_PSEL(QSPI_IO3, 1, 1)>; 92 low-power-enable; 93 }; 94 group2 { 95 psels = <NRF_PSEL(QSPI_CSN, 1, 6)>; 96 low-power-enable; 97 bias-pull-up; 98 }; 99 }; 100 101}; 102