1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	pwm0_default: pwm0_default {
8		group1 {
9			psels = <NRF_PSEL(PWM_OUT0, 1, 7)>;
10		};
11	};
12
13	pwm0_sleep: pwm0_sleep {
14		group1 {
15			psels = <NRF_PSEL(PWM_OUT0, 1, 7)>;
16			low-power-enable;
17		};
18	};
19
20	pwm1_default: pwm1_default {
21		group1 {
22			psels = <NRF_PSEL(PWM_OUT0, 1, 3)>;
23		};
24	};
25
26	pwm1_sleep: pwm1_sleep {
27		group1 {
28			psels = <NRF_PSEL(PWM_OUT0, 1, 3)>;
29			low-power-enable;
30		};
31	};
32
33	uart0_default: uart0_default {
34		group1 {
35			psels = <NRF_PSEL(UART_TX, 0, 6)>,
36				<NRF_PSEL(UART_RX, 0, 8)>,
37				<NRF_PSEL(UART_RTS, 0, 5)>,
38				<NRF_PSEL(UART_CTS, 0, 7)>;
39		};
40	};
41
42	uart0_sleep: uart0_sleep {
43		group1 {
44			psels = <NRF_PSEL(UART_TX, 0, 6)>,
45				<NRF_PSEL(UART_RX, 0, 8)>,
46				<NRF_PSEL(UART_RTS, 0, 5)>,
47				<NRF_PSEL(UART_CTS, 0, 7)>;
48			low-power-enable;
49		};
50	};
51
52	uart1_default: uart1_default {
53		group1 {
54			psels = <NRF_PSEL(UART_TX, 0, 16)>,
55				<NRF_PSEL(UART_RX, 0, 14)>,
56				<NRF_PSEL(UART_RTS, 0, 13)>,
57				<NRF_PSEL(UART_CTS, 0, 15)>;
58		};
59	};
60
61	uart1_sleep: uart1_sleep {
62		group1 {
63			psels = <NRF_PSEL(UART_TX, 0, 16)>,
64				<NRF_PSEL(UART_RX, 0, 14)>,
65				<NRF_PSEL(UART_RTS, 0, 13)>,
66				<NRF_PSEL(UART_CTS, 0, 15)>;
67			low-power-enable;
68		};
69	};
70
71	i2c0_default: i2c0_default {
72		group1 {
73			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
74				<NRF_PSEL(TWIM_SCL, 0, 27)>;
75		};
76	};
77
78	i2c0_sleep: i2c0_sleep {
79		group1 {
80			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
81				<NRF_PSEL(TWIM_SCL, 0, 27)>;
82			low-power-enable;
83		};
84	};
85
86	spi1_default: spi1_default {
87		group1 {
88			psels = <NRF_PSEL(SPIM_SCK, 1, 9)>,
89				<NRF_PSEL(SPIM_MOSI, 1, 8)>,
90				<NRF_PSEL(SPIM_MISO, 0, 4)>;
91		};
92	};
93
94	spi1_sleep: spi1_sleep {
95		group1 {
96			psels = <NRF_PSEL(SPIM_SCK, 1, 9)>,
97				<NRF_PSEL(SPIM_MOSI, 1, 8)>,
98				<NRF_PSEL(SPIM_MISO, 0, 4)>;
99			low-power-enable;
100		};
101	};
102
103	qspi_default: qspi_default {
104		group1 {
105			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
106				<NRF_PSEL(QSPI_IO0, 0, 20)>,
107				<NRF_PSEL(QSPI_IO1, 0, 21)>,
108				<NRF_PSEL(QSPI_IO2, 0, 22)>,
109				<NRF_PSEL(QSPI_IO3, 0, 23)>,
110				<NRF_PSEL(QSPI_CSN, 0, 17)>;
111		};
112	};
113
114	qspi_sleep: qspi_sleep {
115		group1 {
116			psels = <NRF_PSEL(QSPI_SCK, 0, 19)>,
117				<NRF_PSEL(QSPI_IO0, 0, 20)>,
118				<NRF_PSEL(QSPI_IO1, 0, 21)>,
119				<NRF_PSEL(QSPI_IO2, 0, 22)>,
120				<NRF_PSEL(QSPI_IO3, 0, 23)>,
121				<NRF_PSEL(QSPI_CSN, 0, 17)>;
122			low-power-enable;
123		};
124	};
125
126};
127