1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	i2c1_default: i2c1_default {
8		group1 {
9			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
10				<NRF_PSEL(TWIM_SCL, 1, 3)>;
11		};
12	};
13
14	i2c1_sleep: i2c1_sleep {
15		group1 {
16			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
17				<NRF_PSEL(TWIM_SCL, 1, 3)>;
18			low-power-enable;
19		};
20	};
21
22	spi2_default: spi2_default {
23		group1 {
24			psels = <NRF_PSEL(SPIM_MISO, 0, 26)>,
25				<NRF_PSEL(SPIM_MOSI, 0, 27)>,
26				<NRF_PSEL(SPIM_SCK, 0, 28)>;
27		};
28	};
29
30	spi2_sleep: spi2_sleep {
31		group1 {
32			psels = <NRF_PSEL(SPIM_MISO, 0, 26)>,
33				<NRF_PSEL(SPIM_MOSI, 0, 27)>,
34				<NRF_PSEL(SPIM_SCK, 0, 28)>;
35			low-power-enable;
36		};
37	};
38
39	spi3_default: spi3_default {
40		group1 {
41			psels = <NRF_PSEL(SPIM_SCK, 1, 14)>,
42				<NRF_PSEL(SPIM_MISO, 1, 15)>,
43				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
44		};
45	};
46
47	spi3_sleep: spi3_sleep {
48		group1 {
49			psels = <NRF_PSEL(SPIM_SCK, 1, 14)>,
50				<NRF_PSEL(SPIM_MISO, 1, 15)>,
51				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
52			low-power-enable;
53		};
54	};
55
56	spi4_default: spi4_default {
57		group1 {
58			psels = <NRF_PSEL(SPIM_MISO, 0, 10)>,
59				<NRF_PSEL(SPIM_MOSI, 0, 9)>,
60				<NRF_PSEL(SPIM_SCK, 0, 8)>;
61		};
62	};
63
64	spi4_sleep: spi4_sleep {
65		group1 {
66			psels = <NRF_PSEL(SPIM_MISO, 0, 10)>,
67				<NRF_PSEL(SPIM_MOSI, 0, 9)>,
68				<NRF_PSEL(SPIM_SCK, 0, 8)>;
69			low-power-enable;
70		};
71	};
72
73	uart0_default: uart0_default {
74		group1 {
75			psels = <NRF_PSEL(UART_TX, 0, 20)>,
76				<NRF_PSEL(UART_RX, 0, 22)>,
77				<NRF_PSEL(UART_RTS, 0, 19)>,
78				<NRF_PSEL(UART_CTS, 0, 21)>;
79		};
80	};
81
82	uart0_sleep: uart0_sleep {
83		group1 {
84			psels = <NRF_PSEL(UART_TX, 0, 20)>,
85				<NRF_PSEL(UART_RX, 0, 22)>,
86				<NRF_PSEL(UART_RTS, 0, 19)>,
87				<NRF_PSEL(UART_CTS, 0, 21)>;
88			low-power-enable;
89		};
90	};
91
92	uart1_default: uart1_default {
93		group1 {
94			psels = <NRF_PSEL(UART_TX,  1,  8)>,
95				<NRF_PSEL(UART_RX,  1, 10)>,
96				<NRF_PSEL(UART_RTS, 1,  7)>,
97				<NRF_PSEL(UART_CTS, 1,  9)>;
98		};
99	};
100
101	uart1_sleep: uart1_sleep {
102		group1 {
103			psels = <NRF_PSEL(UART_TX,  1,  8)>,
104				<NRF_PSEL(UART_RX,  1, 10)>,
105				<NRF_PSEL(UART_RTS, 1,  7)>,
106				<NRF_PSEL(UART_CTS, 1,  9)>;
107			low-power-enable;
108		};
109	};
110
111	pwm0_default: pwm0_default {
112		group1 {
113			psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
114		};
115	};
116
117	pwm0_sleep: pwm0_sleep {
118		group1 {
119			psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
120			low-power-enable;
121		};
122	};
123
124	qspi_default: qspi_default {
125		group1 {
126			psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
127				<NRF_PSEL(QSPI_IO0, 0, 13)>,
128				<NRF_PSEL(QSPI_IO1, 0, 14)>,
129				<NRF_PSEL(QSPI_IO2, 0, 15)>,
130				<NRF_PSEL(QSPI_IO3, 0, 16)>,
131				<NRF_PSEL(QSPI_CSN, 0, 18)>;
132		};
133	};
134
135	qspi_sleep: qspi_sleep {
136		group1 {
137			psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
138				<NRF_PSEL(QSPI_IO0, 0, 13)>,
139				<NRF_PSEL(QSPI_IO1, 0, 14)>,
140				<NRF_PSEL(QSPI_IO2, 0, 15)>,
141				<NRF_PSEL(QSPI_IO3, 0, 16)>,
142				<NRF_PSEL(QSPI_CSN, 0, 18)>;
143			low-power-enable;
144		};
145	};
146
147};
148