1/*
2 * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <arm/armv8.1-m.dtsi>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/input/input-event-codes.h>
12#include <mem.h>
13#include "mps3_common.dtsi"
14
15/ {
16	compatible = "arm,mps3-an555";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	chosen {
21		zephyr,console = &uart0;
22		zephyr,shell-uart = &uart0;
23		zephyr,sram = &ram;
24		zephyr,flash = &code;
25	};
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu@0 {
32			device_type = "cpu";
33			compatible = "arm,cortex-m85";
34			reg = <0>;
35			#address-cells = <1>;
36			#size-cells = <1>;
37
38			mpu: mpu@e000ed90 {
39				compatible = "arm,armv8.1m-mpu";
40				reg = <0xe000ed90 0x40>;
41			};
42		};
43	};
44
45	/* We utilize the secure addresses, if you subtract 0x10000000
46	 * you'll get the non-secure alias
47	 */
48	itcm: itcm@0 {
49		compatible = "zephyr,memory-region";
50		reg = <0x0 DT_SIZE_K(32)>;
51		zephyr,memory-region = "ITCM";
52	};
53
54	sram: sram@1000000 {
55		compatible = "zephyr,memory-region", "mmio-sram";
56		reg = <0x1000000 DT_SIZE_M(2)>;
57		zephyr,memory-region = "SRAM";
58	};
59
60	dtcm: dtcm@20000000 {
61		compatible = "zephyr,memory-region";
62		reg = <0x20000000 DT_SIZE_K(512)>;
63		zephyr,memory-region = "DTCM";
64	};
65
66	isram: sram@21000000 {
67		compatible = "zephyr,memory-region", "mmio-sram";
68		reg = <0x21000000 DT_SIZE_M(4)>;
69		zephyr,memory-region = "ISRAM";
70	};
71
72	reserved-memory {
73		#address-cells = <1>;
74		#size-cells = <1>;
75		ranges;
76
77		/* The memory regions defined below must match what the TF-M
78		 * project has defined for that board - a single image boot is
79		 * assumed. Please see the memory layout in:
80		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone310/common/partition/flash_layout.h
81		 */
82
83		code: memory@1000000 {
84			reg = <0x01000000 DT_SIZE_M(2)>;
85		};
86
87		ram: memory@21000000 {
88			reg = <0x21000000 DT_SIZE_M(4)>;
89		};
90	};
91
92	soc {
93		peripheral@40000000 {
94			#address-cells = <1>;
95			#size-cells = <1>;
96			ranges = <0x0 0x40000000 0x10000000>;
97
98			#include "mps3_common_soc_peripheral.dtsi"
99		};
100	};
101};
102