1/*
2 * Copyright (c) 2018-2021 Linaro Limited
3 * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8/dts-v1/;
9
10#include <arm/armv8.1-m.dtsi>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13#include <mem.h>
14#include "mps3_common.dtsi"
15
16/ {
17	compatible = "arm,mps3-an547";
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	chosen {
22		zephyr,console = &uart0;
23		zephyr,shell-uart = &uart0;
24		zephyr,sram = &ram;
25		zephyr,flash = &code;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu@0 {
33			device_type = "cpu";
34			compatible = "arm,cortex-m55";
35			reg = <0>;
36			#address-cells = <1>;
37			#size-cells = <1>;
38
39			mpu: mpu@e000ed90 {
40				compatible = "arm,armv8.1m-mpu";
41				reg = <0xe000ed90 0x40>;
42			};
43		};
44	};
45
46	/* We utilize the secure addresses, if you subtract 0x10000000
47	 * you'll get the non-secure alias
48	 */
49	itcm: itcm@0 {
50		compatible = "zephyr,memory-region";
51		reg = <0x0 DT_SIZE_K(512)>;
52		zephyr,memory-region = "ITCM";
53	};
54
55	sram: sram@1000000 {
56		compatible = "zephyr,memory-region", "mmio-sram";
57		reg = <0x1000000 DT_SIZE_M(2)>;
58		zephyr,memory-region = "SRAM";
59	};
60
61	dtcm: dtcm@20000000 {
62		compatible = "zephyr,memory-region";
63		reg = <0x20000000 DT_SIZE_K(512)>;
64		zephyr,memory-region = "DTCM";
65	};
66
67	isram: sram@21000000 {
68		compatible = "zephyr,memory-region", "mmio-sram";
69		reg = <0x21000000 DT_SIZE_M(4)>;
70		zephyr,memory-region = "ISRAM";
71	};
72
73	reserved-memory {
74		#address-cells = <1>;
75		#size-cells = <1>;
76		ranges;
77
78		/* The memory regions defined below must match what the TF-M
79		 * project has defined for that board - a single image boot is
80		 * assumed. Please see the memory layout in:
81		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
82		 */
83
84		code: memory@28080000 {
85			reg = <0x28080000 DT_SIZE_K(512)>;
86		};
87
88		ram: memory@21020000 {
89			reg = <0x21020000 DT_SIZE_M(2)>;
90		};
91	};
92
93	soc {
94		peripheral@40000000 {
95			#address-cells = <1>;
96			#size-cells = <1>;
97			ranges = <0x0 0x40000000 0x10000000>;
98
99			#include "mps3_common_soc_peripheral.dtsi"
100		};
101	};
102};
103