1/*
2 * Copyright (c) 2018-2019 Linaro Limited
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <mem.h>
10#include <arm/armv8-m.dtsi>
11#include <zephyr/dt-bindings/i2c/i2c.h>
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13
14/ {
15	compatible = "arm,mps2";
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		led0 = &led_0;
21		led1 = &led_1;
22		sw0 = &user_button_0;
23		sw1 = &user_button_1;
24		watchdog0 = &wdog0;
25	};
26
27	chosen {
28		zephyr,console = &uart0;
29		zephyr,shell-uart = &uart0;
30		zephyr,sram = &ram;
31		zephyr,flash = &code;
32	};
33
34	leds {
35		compatible = "gpio-leds";
36		led_0: led_0 {
37			gpios = <&gpio_led0 0>;
38			label = "USERLED0";
39		};
40		led_1: led_1 {
41			gpios = <&gpio_led0 1>;
42			label = "USERLED1";
43		};
44	};
45
46	gpio_keys {
47		compatible = "gpio-keys";
48		user_button_0: button_0 {
49			label = "USERPB0";
50			gpios = <&gpio_button 0>;
51			zephyr,code = <INPUT_KEY_0>;
52		};
53		user_button_1: button_1 {
54			label = "USERPB1";
55			gpios = <&gpio_button 1>;
56			zephyr,code = <INPUT_KEY_1>;
57		};
58	};
59
60	cpus {
61		#address-cells = <1>;
62		#size-cells = <0>;
63
64		cpu@0 {
65			device_type = "cpu";
66			compatible = "arm,cortex-m33";
67			reg = <0>;
68			#address-cells = <1>;
69			#size-cells = <1>;
70
71			mpu: mpu@e000ed90 {
72				compatible = "arm,armv8m-mpu";
73				reg = <0xe000ed90 0x40>;
74			};
75		};
76	};
77
78	/*
79	 * The memory regions defined below are according to AN521:
80	 * https://documentation-service.arm.com/static/5fa12fe9b1a7c5445f29017f
81	 *
82	 * Please see tables mentioned in individual comments below for details.
83	 */
84
85	ssram1: memory@0 {
86		/* Table 3-2, row 1. */
87		compatible = "zephyr,memory-region", "mmio-sram";
88		reg = <0x0 DT_SIZE_M(4)>;
89		zephyr,memory-region = "SSRAM1";
90	};
91
92	ssram2_3: memory@28000000 {
93		/* Table 3-4, rows 8 and 9. */
94		compatible = "zephyr,memory-region", "mmio-sram";
95		reg = <0x28000000 DT_SIZE_M(4)>;
96		zephyr,memory-region = "SSRAM2_3";
97	};
98
99	psram: memory@80000000 {
100		/* Table 3-6, row 1. */
101		device_type = "memory";
102		reg = <0x80000000 DT_SIZE_M(16)>;
103	};
104
105	reserved-memory {
106		#address-cells = <1>;
107		#size-cells = <1>;
108		ranges;
109
110		/* The code memory region defined below is selected to remain
111		 * compatible with what TF-M has defined for a single boot image,
112		 * where 468 KB memory at the bottom of the 4 MB code region is
113		 * marked as 'Unused'. Please see the memory layout in:
114		 *
115		 * https://github.com/zephyrproject-rtos/trusted-firmware-m/blob/master/platform/ext/target/arm/mps2/an521/partition/flash_layout.h
116		 */
117
118		code: memory@38B000 {
119			reg = <0x0038B000 DT_SIZE_K(468)>;
120		};
121
122		/* This ram memory region's base address is chosen to avoid
123		 * conflict with the mps2_an521_ns board's RAM region.
124		 *
125		 * Its available address space must be compatible with what
126		 * TF-M assigns to NS firmware.
127		 */
128		ram: memory@28180000 {
129			reg = <0x28180000 DT_SIZE_K(512)>;
130		};
131	};
132
133	soc {
134		peripheral@40000000 {
135			#address-cells = <1>;
136			#size-cells = <1>;
137			ranges = <0x0 0x40000000 0x10000000>;
138
139			#include "mps2_an521-common.dtsi"
140		};
141	};
142};
143
144&nvic {
145	arm,num-irq-priority-bits = <3>;
146};
147