1/*
2 * Copyright (c) 2023 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
8#include "apollo4p_evb_connector.dtsi"
9
10&pinctrl {
11	uart0_default: uart0_default {
12		group1 {
13			pinmux = <UART0TX_P60>;
14		};
15		group2 {
16			pinmux = <UART0RX_P47>;
17			input-enable;
18		};
19	};
20	itm_default: itm_default {
21		group1 {
22			pinmux = <SWO_P28>;
23		};
24	};
25	adc0_default: adc0_default{
26		group1 {
27			pinmux = <ADCSE4_P15>, <ADCSE7_P12>;
28			drive-strength = "0.1";
29		};
30	};
31	i2c0_default: i2c0_default {
32		group1 {
33			pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
34			drive-open-drain;
35			drive-strength = "0.5";
36			bias-pull-up;
37		};
38	};
39	i2c1_default: i2c1_default {
40		group1 {
41			pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
42			drive-open-drain;
43			drive-strength = "0.5";
44			bias-pull-up;
45		};
46	};
47	i2c2_default: i2c2_default {
48		group1 {
49			pinmux = <M2SCL_P25>, <M2SDAWIR3_P26>;
50			drive-open-drain;
51			drive-strength = "0.5";
52			bias-pull-up;
53		};
54	};
55	i2c3_default: i2c3_default {
56		group1 {
57			pinmux = <M3SCL_P31>, <M3SDAWIR3_P32>;
58			drive-open-drain;
59			drive-strength = "0.5";
60			bias-pull-up;
61		};
62	};
63	i2c4_default: i2c4_default {
64		group1 {
65			pinmux = <M4SCL_P34>, <M4SDAWIR3_P35>;
66			drive-open-drain;
67			drive-strength = "0.5";
68			bias-pull-up;
69		};
70	};
71	i2c5_default: i2c5_default {
72		group1 {
73			pinmux = <M5SCL_P47>, <M5SDAWIR3_P48>;
74			drive-open-drain;
75			drive-strength = "0.5";
76			bias-pull-up;
77		};
78	};
79	i2c6_default: i2c6_default {
80		group1 {
81			pinmux = <M6SCL_P61>, <M6SDAWIR3_P62>;
82			drive-open-drain;
83			drive-strength = "0.5";
84			bias-pull-up;
85		};
86	};
87	i2c7_default: i2c7_default {
88		group1 {
89			pinmux = <M7SCL_P22>, <M7SDAWIR3_P23>;
90			drive-open-drain;
91			drive-strength = "0.5";
92			bias-pull-up;
93		};
94	};
95	spi0_default: spi0_default {
96		group1 {
97			pinmux = <M0SCK_P5>, <M0MISO_P7>, <M0MOSI_P6>;
98		};
99	};
100	spi1_default: spi1_default {
101		group1 {
102			pinmux = <M1SCK_P8>, <M1MISO_P10>, <M1MOSI_P9>;
103		};
104	};
105	spi2_default: spi2_default {
106		group1 {
107			pinmux = <M2SCK_P25>, <M2MISO_P27>, <M2MOSI_P26>;
108		};
109	};
110	spi3_default: spi3_default {
111		group1 {
112			pinmux = <M3SCK_P31>, <M3MISO_P33>, <M3MOSI_P32>;
113		};
114	};
115	spi4_default: spi4_default {
116		group1 {
117			pinmux = <M4SCK_P34>, <M4MISO_P36>, <M4MOSI_P35>;
118		};
119	};
120	spi5_default: spi5_default {
121		group1 {
122			pinmux = <M5SCK_P47>, <M5MISO_P49>, <M5MOSI_P48>;
123		};
124	};
125	spi6_default: spi6_default {
126		group1 {
127			pinmux = <M6SCK_P61>, <M6MISO_P63>, <M6MOSI_P62>;
128		};
129	};
130	spi7_default: spi7_default {
131		group1 {
132			pinmux = <M7SCK_P22>, <M7MISO_P24>, <M7MOSI_P23>;
133		};
134	};
135	mspi0_default: mspi0_default{
136		group1 {
137			pinmux = <MSPI0_0_P64>,
138				 <MSPI0_1_P65>,
139				 <MSPI0_8_P72>;
140		};
141		group2 {
142			pinmux = <NCE57_P57>;
143			drive-push-pull;
144			drive-strength = "0.5";
145			ambiq,iom-nce-module = <32>;
146		};
147	};
148	mspi1_default: mspi1_default{
149		group1 {
150			pinmux = <MSPI1_0_P37>,
151				 <MSPI1_1_P38>,
152				 <MSPI1_8_P45>;
153		};
154		group2 {
155			pinmux = <NCE56_P56>;
156			drive-push-pull;
157			drive-strength = "0.5";
158			ambiq,iom-nce-module = <34>;
159		};
160	};
161	mspi2_default: mspi2_default{
162		group1 {
163			pinmux = <MSPI2_0_P74>,
164				 <MSPI2_1_P75>,
165				 <MSPI2_8_P82>;
166		};
167		group2 {
168			pinmux = <NCE0_P0>;
169			drive-push-pull;
170			drive-strength = "0.5";
171			ambiq,iom-nce-module = <36>;
172		};
173	};
174};
175