1/*
2 * Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
8#include "apollo3p_evb_connector.dtsi"
9
10&pinctrl {
11	uart0_default: uart0_default {
12		group1 {
13			pinmux = <UART0TX_P22>;
14		};
15		group2 {
16			pinmux = <UART0RX_P23>;
17			input-enable;
18		};
19	};
20	itm_default: itm_default {
21		group1 {
22			pinmux = <SWO_P41>;
23		};
24	};
25	i2c0_default: i2c0_default {
26		group1 {
27			pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
28			drive-open-drain;
29			drive-strength = "0.5";
30			bias-pull-up;
31		};
32	};
33	i2c1_default: i2c1_default {
34		group1 {
35			pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
36			drive-open-drain;
37			drive-strength = "0.5";
38			bias-pull-up;
39		};
40	};
41	i2c2_default: i2c2_default {
42		group1 {
43			pinmux = <M2SCL_P27>, <M2SDAWIR3_P25>;
44			drive-open-drain;
45			drive-strength = "0.5";
46			bias-pull-up;
47		};
48	};
49	i2c3_default: i2c3_default {
50		group1 {
51			pinmux = <M3SCL_P42>, <M3SDAWIR3_P43>;
52			drive-open-drain;
53			drive-strength = "0.5";
54			bias-pull-up;
55		};
56	};
57	i2c4_default: i2c4_default {
58		group1 {
59			pinmux = <M4SCL_P39>, <M4SDAWIR3_P40>;
60			drive-open-drain;
61			drive-strength = "0.5";
62			bias-pull-up;
63		};
64	};
65	i2c5_default: i2c5_default {
66		group1 {
67			pinmux = <M5SCL_P48>, <M5SDAWIR3_P49>;
68			drive-open-drain;
69			drive-strength = "0.5";
70			bias-pull-up;
71		};
72	};
73	spid0_default: spid0_default {
74		group1 {
75			pinmux = <SLSCK_P0>, <SLMISO_P2>, <SLMOSI_P1>, <SLNCE_P3>;
76		};
77	};
78	spi0_default: spi0_default {
79		group1 {
80			pinmux = <M0SCK_P5>, <M0MISO_P6>, <M0MOSI_P7>;
81		};
82	};
83	spi1_default: spi1_default {
84		group1 {
85			pinmux = <M1SCK_P8>, <M1MISO_P9>, <M1MOSI_P10>;
86		};
87	};
88	spi2_default: spi2_default {
89		group1 {
90			pinmux = <M2SCK_P27>, <M2MISO_P25>, <M2MOSI_P28>;
91		};
92	};
93	spi3_default: spi3_default {
94		group1 {
95			pinmux = <M3SCK_P42>, <M3MISO_P43>, <M3MOSI_P38>;
96		};
97	};
98	spi4_default: spi4_default {
99		group1 {
100			pinmux = <M4SCK_P39>, <M4MISO_P40>, <M4MOSI_P44>;
101		};
102	};
103	spi5_default: spi5_default {
104		group1 {
105			pinmux = <M5SCK_P48>, <M5MISO_P49>, <M5MOSI_P47>;
106		};
107	};
108
109	adc0_default: adc0_default{
110		group1 {
111			pinmux = <ADCSE4_P32>, <ADCSE7_P35>;
112			drive-strength = "0.1";
113		};
114	};
115
116	mspi0_default: mspi0_default{
117		group1 {
118			pinmux = <MSPI0_0_P22>,
119				 <MSPI0_1_P26>,
120				 <MSPI0_2_P4>,
121				 <MSPI0_3_P23>,
122				 <MSPI0_8_P24>;
123		};
124		group2 {
125			pinmux = <NCE37_P37>;
126			drive-push-pull;
127			drive-strength = "0.5";
128			ambiq,iom-mspi = <0>;
129			ambiq,iom-nce-module = <0>;
130			ambiq,iom-num = <0>;
131		};
132	};
133	mspi1_default: mspi1_default{
134		group1 {
135			pinmux = <MSPI1_0_P51>,
136				 <MSPI1_1_P52>,
137				 <MSPI1_2_P53>,
138				 <MSPI1_3_P54>,
139				 <MSPI1_4_P55>,
140				 <MSPI1_5_P56>,
141				 <MSPI1_6_P57>,
142				 <MSPI1_7_P58>,
143				 <MSPI1_8_P59>;
144		};
145		group2 {
146			pinmux = <NCE50_P50>;
147			drive-push-pull;
148			drive-strength = "0.5";
149			ambiq,iom-mspi = <0>;
150			ambiq,iom-nce-module = <0>;
151			ambiq,iom-num = <1>;
152		};
153	};
154	mspi2_default: mspi2_default{
155		group1 {
156			pinmux = <MSPI2_0_P64>,
157				 <MSPI2_1_P65>,
158				 <MSPI2_2_P66>,
159				 <MSPI2_3_P67>,
160				 <MSPI2_4_P68>;
161		};
162		group2 {
163			pinmux = <NCE63_P63>;
164			drive-push-pull;
165			drive-strength = "0.5";
166			ambiq,iom-mspi = <0>;
167			ambiq,iom-nce-module = <0>;
168			ambiq,iom-num = <2>;
169		};
170	};
171
172	bleif_default: bleif_default{
173		group1 {
174			pinmux = <BLEIF_SCK_P30>,
175				 <BLEIF_MISO_P31>,
176				 <BLEIF_MOSI_P32>,
177				 <BLEIF_CSN_P33>,
178				 <BLEIF_STATUS_P35>,
179				 <BLEIF_IRQ_P41>;
180		};
181	};
182};
183