1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9 #include <adi/max32/max32680.dtsi>
10 #include <adi/max32/max32680-pinctrl.dtsi>
11 #include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
14
15/ {
16	 model = "Analog Devices MAX32680EVKIT";
17	 compatible = "adi,max32680evkit";
18
19	 chosen {
20		 zephyr,console = &uart1;
21		 zephyr,shell-uart = &uart1;
22		 zephyr,sram = &sram2;
23		 zephyr,flash = &flash0;
24		 zephyr,display = &st7735;
25	 };
26
27	 leds {
28		 compatible = "gpio-leds";
29		 led1: led_1 {
30			 gpios = <&gpio0 24 GPIO_ACTIVE_LOW>;
31			 label = "Red LED";
32		 };
33		 led2: led_2 {
34			 gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
35			 label = "Blue LED";
36		 };
37	 };
38
39	 buttons {
40		 compatible = "gpio-keys";
41		 pb1: pb1 {
42			 gpios = <&gpio0 26 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
43			 label = "SW1";
44			 zephyr,code = <INPUT_KEY_0>;
45		 };
46		 pb2: pb2 {
47			 gpios = <&gpio0 27 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
48			 label = "SW2";
49			 zephyr,code = <INPUT_KEY_1>;
50		 };
51	 };
52
53	 /* These aliases are provided for compatibility with samples */
54	 aliases {
55		led0 = &led1;
56		led1 = &led2;
57		sw0 = &pb1;
58		sw1 = &pb2;
59		watchdog0 = &wdt0;
60	 };
61
62	 mipi_dbi {
63		compatible = "zephyr,mipi-dbi-spi";
64		/* Enable D/C line for 4wire mode */
65		/* dc-gpios = <&gpio1 7 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>; */
66		spi-dev = <&spi0>;
67		#address-cells = <1>;
68		#size-cells = <0>;
69
70		status = "okay";
71
72		st7735: st7735@0 {
73			compatible = "sitronix,st7735r";
74			mipi-max-frequency = <DT_FREQ_M(6)>;
75			mipi-mode = "MIPI_DBI_MODE_SPI_3WIRE";
76
77			reg = <0>;
78			width = <130>;
79			height = <132>;
80			x-offset = <0>;
81			y-offset = <0>;
82			madctl = <0xc0>;
83			colmod = <0x05>;
84			vmctr1 = <0x51>;
85			pwctr1 = [02 02];
86			pwctr2 = [c5];
87			pwctr3 = [0d 00];
88			pwctr4 = [8d 1a];
89			pwctr5 = [8d ee];
90			frmctr1 = [02 35 36];
91			frmctr2 = [02 35 36];
92			frmctr3 = [02 35 36 02 35 36];
93			gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d];
94			gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d];
95		};
96	};
97};
98
99&uart1 {
100	pinctrl-0 = <&uart1a_tx_p0_13 &uart1a_rx_p0_12>;
101	pinctrl-names = "default";
102	current-speed = <115200>;
103	data-bits = <8>;
104	parity = "none";
105	status = "okay";
106};
107
108&clk_ipo {
109	status = "okay";
110};
111
112&gpio0 {
113	status = "okay";
114};
115
116&gpio1 {
117	status = "okay";
118};
119
120&gpio2 {
121	status = "okay";
122};
123
124&trng {
125	status = "okay";
126};
127
128&i2c0 {
129	status = "okay";
130	pinctrl-0 = <&i2c0a_scl_p0_10 &i2c0a_sda_p0_11>;
131	pinctrl-names = "default";
132};
133
134&i2c1 {
135	status = "okay";
136	pinctrl-0 = <&i2c1a_scl_p0_16 &i2c1a_sda_p0_17>;
137	pinctrl-names = "default";
138};
139
140&dma0 {
141	status = "okay";
142};
143
144&wdt0 {
145	status = "okay";
146};
147
148&spi0 {
149	status = "okay";
150	pinctrl-0 = <&spi0a_mosi_p0_5 &spi0a_miso_p0_6 &spi0a_sck_p0_7 &spi0a_ss0_p0_4>;
151	pinctrl-names = "default";
152};
153
154&spi0a_mosi_p0_5 {
155	power-source=<MAX32_VSEL_VDDIOH>;
156};
157
158&spi0a_sck_p0_7 {
159	power-source=<MAX32_VSEL_VDDIOH>;
160};
161
162&spi0 {
163	status = "okay";
164	pinctrl-0 = <&spi0a_mosi_p0_5 &spi0a_miso_p0_6 &spi0a_sck_p0_7>;
165	pinctrl-names = "default";
166	cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>;
167};
168
169&w1 {
170	pinctrl-0 = <&owm_io_p0_6 &owm_pe_p0_7>;
171	pinctrl-names = "default";
172};
173