1.. zephyr:board:: max32675evkit 2 3Overview 4******** 5The MAX32675 evaluation kit (EV kit) provides a platform for evaluation capabilities of 6the MAX32675 microcontroller, which is a highly integrated, mixed-signal, ultralow-power 7microcontroller designed for industrial and medical sensors. It contains an integrated, low-power 8HART modem which enables the bidirectional transfer of digital data over a current loop, to/from 9industrial sensors for configuration and diagnostics. 10 11The Zephyr port is running on the MAX32675 MCU. 12 13Hardware 14******** 15 16- MAX32675 MCU: 17 18 - Low-Power, High-Performance for IndustrialApplications 19 20 - 100MHz Arm Cortex-M4 with FPU 21 - 384KB Internal Flash 22 - 160KB SRAM 23 - 128kB ECC Enabled 24 - 44.1μA/MHz ACTIVE Mode at 0.9V up to 12MHzCoremark® 25 - 64.5μA/MHz ACTIVE Mode at 1.1V up to 100MHzCoremark 26 - 2.84μA Full Memory Retention Current in BACKUPMode at VDDIO = 3.3V 27 - Ultra-Low-Power Analog Peripherals 28 29 - Optimal Peripheral Mix Provides Platform Scalability 30 31 - Two Sigma-Delta ADCs 32 - 12 Channels, Assignable to Either ADC 33 - Flexible Resolution and Sample Rates (24 Bits at 0.4ksps, 16 Bits at 4ksps) 34 - 12-Bit DAC 35 - On-Die Temperature Sensor 36 - SPI (M/S) 37 - Up to Two I2C 38 - Up to Two UARTs 39 - Up to 23 GPIOs 40 - Up to Five 32-Bit Timers 41 - Two Windowed Watchdog Timers 42 - 8-Channel Standard DMA Controller 43 - One I2S Slave for Digital Audio Interface 44 45 - Robust Security and Reliability 46 47 - TRNG Compliant to SP800-90B 48 - Secure Nonvolatile Key Storage and AES-128/192/256 49 - Secure Bootloader to Protect IP/Firmware 50 - Wide, -40°C to +105°C Operating TemperatureRange 51 52 53- Benefits and Features of MAX32675EVKIT: 54 55 - HART Compatible Secondary Master with the Ability to Connect to Existing 4-20mA Current Loop and Communicate with HART Enabled Devices 56 - USB 2.0 Micro B to Serial UART 57 - Two On-Board, High-Precision Voltage References 58 - All GPIOs Signals Accessed Through 0.1in Headers 59 - Access to 4 Analog Inputs Through SMA Connectors Configured as Differential 60 - Access to 8 Analog Inputs Through 0.1in Headers Configured as Single-Ended 61 - DAC Output Accessed Through SMA Connector or Test Point 62 - 10-Pin SWD and Connector 63 - Board Power Provided by USB Port 64 - On-Board 1.0V, 1.8V, and 3.3V LDO Regulators 65 - Individual Power Measurement on all IC Rails Through Jumpers 66 - Two General-Purpose LEDs and Two General-Purpose Pushbutton Switches 67 68Supported Features 69================== 70 71Below interfaces are supported by Zephyr on MAX32675EVKIT. 72 73+-----------+------------+-------------------------------------+ 74| Interface | Controller | Driver/Component | 75+===========+============+=====================================+ 76| NVIC | on-chip | nested vector interrupt controller | 77+-----------+------------+-------------------------------------+ 78| SYSTICK | on-chip | systick | 79+-----------+------------+-------------------------------------+ 80| CLOCK | on-chip | clock and reset control | 81+-----------+------------+-------------------------------------+ 82| GPIO | on-chip | gpio | 83+-----------+------------+-------------------------------------+ 84| UART | on-chip | serial | 85+-----------+------------+-------------------------------------+ 86| TRNG | on-chip | entropy | 87+-----------+------------+-------------------------------------+ 88| SPI | on-chip | spi | 89+-----------+------------+-------------------------------------+ 90| DMA | on-chip | dma controller | 91+-----------+------------+-------------------------------------+ 92| I2C | on-chip | i2c | 93+-----------+------------+-------------------------------------+ 94| PWM | on-chip | pwm | 95+-----------+------------+-------------------------------------+ 96| Flash | on-chip | flash | 97+-----------+------------+-------------------------------------+ 98 99Connections and IOs 100=================== 101 102+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 103| Name | Name | Settings | Description | 104+===========+===============+===============+==================================================================================================+ 105| JP1 | P1_9 | | | 106| | | +-----------+ | +-------------------------------------------------------------------------------+ | 107| | | | Open | | | Disconnects red LED D1 from P1_9. | | 108| | | +-----------+ | +-------------------------------------------------------------------------------+ | 109| | | | Closed | | | Connects red LED D1 to P1_9. | | 110| | | +-----------+ | +-------------------------------------------------------------------------------+ | 111| | | | | 112+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 113| JP2 | P1_10 | +-----------+ | +-------------------------------------------------------------------------------+ | 114| | | | Open | | | Disconnects green LED D2 from P1_10. | | 115| | | +-----------+ | +-------------------------------------------------------------------------------+ | 116| | | | Closed | | | Connects green LED D2 to P1_10. | | 117| | | +-----------+ | +-------------------------------------------------------------------------------+ | 118| | | | | 119+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 120| JP3 | I2C_SCLK | +-----------+ | +-------------------------------------------------------------------------------+ | 121| | | | Open | | | Disconnects 3V3 from I2C_SCLK. | | 122| | | +-----------+ | +-------------------------------------------------------------------------------+ | 123| | | | Closed | | | Connects 3V3 to I2C0_SCLK. | | 124| | | +-----------+ | +-------------------------------------------------------------------------------+ | 125| | | | | 126+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 127| JP4 | I2C_SDA | +-----------+ | +-------------------------------------------------------------------------------+ | 128| | | | Open | | | Disconnects 3V3 to I2C_SDA. | | 129| | | +-----------+ | +-------------------------------------------------------------------------------+ | 130| | | | Closed | | | Connects 3V3 to I2C_SDA. | | 131| | | +-----------+ | +-------------------------------------------------------------------------------+ | 132| | | | | 133+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 134| JP5 | UART0_RX | +-----------+ | +-------------------------------------------------------------------------------+ | 135| | | | Open | | | Disconnects UART0_RX (P0.8) from the SWD connector. | | 136| | | +-----------+ | +-------------------------------------------------------------------------------+ | 137| | | | Closed | | | Connects UART0_RX (P0.8) to the SWD connector. | | 138| | | +-----------+ | +-------------------------------------------------------------------------------+ | 139| | | | | 140+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 141| JP6 | UART0_TX | +-----------+ | +-------------------------------------------------------------------------------+ | 142| | | | Open | | | Disonnects UART0_TX (P0.9) from the SWD connector. | | 143| | | +-----------+ | +-------------------------------------------------------------------------------+ | 144| | | | Closed | | | Connects UART0_TX (P0.9) to the SWD connector. | | 145| | | +-----------+ | +-------------------------------------------------------------------------------+ | 146| | | | | 147+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 148| JP7 | REF0N | +-----------+ | +-------------------------------------------------------------------------------+ | 149| | | | Open | | | Disconnects REF0N from ground. | | 150| | | +-----------+ | +-------------------------------------------------------------------------------+ | 151| | | | Closed | | | Connects REF0N to ground. | | 152| | | +-----------+ | +-------------------------------------------------------------------------------+ | 153| | | | | 154+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 155| JP8 | REF1N | +-----------+ | +-------------------------------------------------------------------------------+ | 156| | | | Open | | | Disconnects REF1N from ground. | | 157| | | +-----------+ | +-------------------------------------------------------------------------------+ | 158| | | | Closed | | | Connects REF1N to ground. | | 159| | | +-----------+ | +-------------------------------------------------------------------------------+ | 160| | | | | 161+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 162| JP9 | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | 163| | | HART_IN | | | Open | | | Disconnects TX of USB - serial bridge from HART_IN (P0.15). | | 164| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | 165| | | HART_IN | | | 1-2 | | | Connects TX of USB - serial bridge to HART_IN (P0.15). | | 166| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | 167| | | HART_OUT | | | Open | | | Disconnects RX of USB - serial bridge from HART_OUT (P0.14). | | 168| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | 169| | | HART_OUT | | | 3-4 | | | Connects RX of USB - serial bridge to HART_OUT (P0.14). | | 170| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | 171| | | HART_RTS | | | Open | | | Disconnects RTS of USB - serial bridge from HART_RTS (P1.8). | | 172| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | 173| | | HART_RTS | | | 4-5 | | | Connects TX of USB - serial bridge to HART_RTS (P1.8). | | 174| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | 175| | | HART_OCD | | | Open | | | Disconnects RTS of USB - serial bridge from HART_OCD (P0.16). | | 176| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | 177| | | HART_OCD | | | 7-8 | | | Connects TX of USB - serial bridge to HART_OCD (P0.16). | | 178| | +-----------+ | +-----------+ | +-------------------------------------------------------------------------------+ | 179| | | | | 180+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 181| JP10 | SWD_CLK | +-----------+ | +-------------------------------------------------------------------------------+ | 182| | | | Open | | | Disconnects boot load enable circuit from SWD_CLK (P0.1). | | 183| | | +-----------+ | +-------------------------------------------------------------------------------+ | 184| | | | Closed | | | Connects boot load enable circuit to SWD_CLK (P0.1). | | 185| | | +-----------+ | +-------------------------------------------------------------------------------+ | 186| | | | | 187+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 188| JP11 | FSK_IN | +-----------+ | +-------------------------------------------------------------------------------+ | 189| | | | Open | | | Disconnects FSK_IN from HART analog circuitry. | | 190| | | +-----------+ | +-------------------------------------------------------------------------------+ | 191| | | | Closed | | | Connects FSK_IN to HART analog circuitry. | | 192| | | +-----------+ | +-------------------------------------------------------------------------------+ | 193| | | | | 194+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 195| JP12 | FSK_OUT | +-----------+ | +-------------------------------------------------------------------------------+ | 196| | | | Open | | | Disconnects FSK_OUT from HART analog circuitry. | | 197| | | +-----------+ | +-------------------------------------------------------------------------------+ | 198| | | | Closed | | | Connects FSK_OUT to HART analog circuitry. | | 199| | | +-----------+ | +-------------------------------------------------------------------------------+ | 200| | | | | 201+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 202| JP13 | RCV_FSK | +-----------+ | +-------------------------------------------------------------------------------+ | 203| | | | Open | | | Disconnects RCV_FSK from CC LOOP. | | 204| | | +-----------+ | +-------------------------------------------------------------------------------+ | 205| | | | Closed | | | Connects RCV_FSK to CC LOOP. | | 206| | | +-----------+ | +-------------------------------------------------------------------------------+ | 207| | | | | 208+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 209| JP14 | RCV_FSK | +-----------+ | +--------------------------------------------------------------------------------+ | 210| | | | Open | | | Disconnects RCV_FSK from XFMR LOOP. | | 211| | | +-----------+ | +--------------------------------------------------------------------------------+ | 212| | | | Closed | | | Connects RCV_FSK to XFMR LOOP. | | 213| | | +-----------+ | +--------------------------------------------------------------------------------+ | 214| | | | | 215+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 216| JP15 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ | 217| | | | Open | | | Disconnects 249Ω resistor shunt from CC LOOP. | | 218| | | +-----------+ | +-------------------------------------------------------------------------------+ | 219| | | | Closed | | | Connects 249Ω resistor shunt to CC LOOP. | | 220| | | +-----------+ | +-------------------------------------------------------------------------------+ | 221| | | | | 222+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 223| JP16 | N/A | N/A | N/A | 224+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 225| JP17 | N/A | N/A | N/A | 226+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 227| JP18 | N/A | N/A | N/A | 228+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 229| JP19 | HART_RTS | +-----------+ | +-------------------------------------------------------------------------------+ | 230| | | | Open | | | Enables HART_RTS optical transceiver. | | 231| | | +-----------+ | +-------------------------------------------------------------------------------+ | 232| | | | Closed | | | Bypasses HART_RTS optical transceiver. | | 233| | | +-----------+ | +-------------------------------------------------------------------------------+ | 234| | | | | 235+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 236| JP20 | RLOAD | +-----------+ | +-------------------------------------------------------------------------------+ | 237| | | | Open | | | Disconnects 249Ω resistor shunt from XFMR LOOP. | | 238| | | +-----------+ | +-------------------------------------------------------------------------------+ | 239| | | | Closed | | | Connects 249Ω resistor shunt to XFMR LOOP. | | 240| | | +-----------+ | +-------------------------------------------------------------------------------+ | 241| | | | | 242+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 243| JP21 | VDDIO | +-----------+ | +-------------------------------------------------------------------------------+ | 244| | | | Open | | | Disconnects power from VDDIO. | | 245| | | +-----------+ | +-------------------------------------------------------------------------------+ | 246| | | | Closed | | | Connects power to VDDIO. | | 247| | | +-----------+ | +-------------------------------------------------------------------------------+ | 248| | | | | 249+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 250| JP22 | VDDA | +-----------+ | +-------------------------------------------------------------------------------+ | 251| | | | Open | | | Disconnects power from VDDA. | | 252| | | +-----------+ | +-------------------------------------------------------------------------------+ | 253| | | | Closed | | | Connects power to VDDA. | | 254| | | +-----------+ | +-------------------------------------------------------------------------------+ | 255| | | | | 256+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 257| JP23 | VDD18 | +-----------+ | +-------------------------------------------------------------------------------+ | 258| | | | Open | | | Disconnects power from VDD18. | | 259| | | +-----------+ | +-------------------------------------------------------------------------------+ | 260| | | | Closed | | | Connects power to VDD18. | | 261| | | +-----------+ | +-------------------------------------------------------------------------------+ | 262| | | | | 263+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 264| JP24 | VCORE | +-----------+ | +-------------------------------------------------------------------------------+ | 265| | | | Open | | | Disconnects power from VCORE. | | 266| | | +-----------+ | +-------------------------------------------------------------------------------+ | 267| | | | Closed | | | Connects power to VCORE. | | 268| | | +-----------+ | +-------------------------------------------------------------------------------+ | 269| | | | | 270+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 271| JP25 | REF0P | +-----------+ | +-------------------------------------------------------------------------------+ | 272| | | | 2-1 | | | Connects OB_VREF to REF0P. | | 273| | | +-----------+ | +-------------------------------------------------------------------------------+ | 274| | | | 2-3 | | | Connects INT_VREF to REF0P. | | 275| | | +-----------+ | +-------------------------------------------------------------------------------+ | 276| | | | | 277+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 278| JP26 | REF1P | +-----------+ | +-------------------------------------------------------------------------------+ | 279| | | | 2-1 | | | Connects OB_VREF to REF1P. | | 280| | | +-----------+ | +-------------------------------------------------------------------------------+ | 281| | | | 2-3 | | | Connects INT_VREF to REF1P. | | 282| | | +-----------+ | +-------------------------------------------------------------------------------+ | 283| | | | | 284+-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+ 285 286 287Detailed Description of Hardware 288================================ 289 290HART Interface 291************** 292The HART circuitry acts as a secondary master with the ability to connect to an existing 4mA–20mA 293current loop and communicates with HART-enabled devices. Connection to a capacitance coupled loop 294through JH8 and a transformer loop is through JH9. HART communication to the MAX32675 is through 295the USB connector CN1. 296 297USB-to-HART Interface 298********************* 299The EV kit provides a USB-to-HART bridge chip, FTDI FT231. This bridge eliminates the requirement 300for a physical RS-232 COM port. Instead, the IC’s HART access is through the Micro-USB type-B 301connector, CN1. Virtual COM port drivers and guides for installing Windows® drivers are available 302at the FTDI chip website. 303 304Power Supply 305************ 306The EV kit is powered by +5V that is made available through VBUS on the Micro-USB type-B 307connector CN1. A blue LED (D5) illuminates when the board is powered. Green LEDs (D6), (D7), 308and (D8) illuminate when the 3V3, 1V8, and 1V0 LDOs are powered, respectively. 309 310Current Monitoring 311****************** 312Two pin headers provide convenient current monitoring points for VDDIO EN (JP21), 313VDDA EN (JP22), VDD18 EN (JP23), and VCORE (JP24). 314To accurately achieve the low-power current values, the EVkit needs to be configured 315such that no outside influence (i.e., pullups, external clock, debugger connector, etc.) 316causes a current source or sink on that GPIO. 317 318Clocking 319******** 320The MAX32675 clocking is provided by an external 16MHz crystal (Y1). 321 322Voltage Reference 323***************** 324The differential reference inputs REF0 and REF1 can be sourced by an internal reference (INT_VREF) 325or a higher precision external reference source, MAX6071. 326This is selected by jumpers JP25 and JP26. 327 328UART Interface 329************** 330The EV kit provides a USB-to-UART bridge chip (the FTDI FT230XS-R). This bridge eliminates 331the requirement for a physical RS-232 COM port. Instead, the IC’s UART access is through 332the Micro USB type-B connector (CN1). The USB-to-UART bridge can be connected to the IC’s UART0 333or LPUART0 with jumpers JP10 (RX0) and JP11 (TX0). Virtual COM port drivers and guides for 334installing Windows® drivers are available on the FTDI Chip website. 335 336Boot Loader 337*********** 338Boot load is activated by boot load enable slide switch SW5. 339 340GPIO and Alternate Function Headers 341*********************************** 342GPIO and alternate function signals from the MAX32675 can be accessed through 0.1in 343spaced headers JH1, JH2, JH3, and JH4. 344 345Analog Input Access 346******************* 347Analog inputs (AIN0–AIN3) can be accessed differentially from SMA connectors J2 and J3 or 348separately from TP10, TP12, TP15, and TP16, respectively. Analog inputs (AIN4–AIN11) can be 349accessed through 0.1in spaced headers JH5 and JH6. 350 351I2C Pullups 352*********** 353The I2C port can independently pulled up to 3V3 through JP3 (I2C_SCL) and JP4 (I2C_SDA). 354 355Reset Pushbutton 356**************** 357The IC can be reset by pushbutton SW3. 358 359Indicator LEDs 360************** 361General-purpose indicators LED D1 (red) is connected to GPIO P1.9 and LED D2 (green) is connected 362to GPIO P1.10. 363 364GPIO Pushbutton Switches 365************************ 366The two general-purpose pushbuttons (SW1 and SW2) are connected to GPIO P1.11 and P1.12, 367respectively. If the pushbutton is pressed, the attached port pin is pulled low. 368 369 370Programming and Debugging 371************************* 372 373Flashing 374======== 375 376SWD debug can be accessed through an Arm Cortex 10-pin connector (J5). 377Logic levels are set to 3V3 by default, but they can be set to 1.8V if TP5 (VDD_VDDA_EXT) 378is supplied externally. Be sure to remove jumper JP15 (LDO_DUT_EN) to disconnect 379the 3.3V LDO if supplying VDD and VDDA externally. 380 381Once the debug probe is connected to your host computer, then you can simply run the 382``west flash`` command to write a firmware image into flash. 383 384.. note:: 385 386 This board uses OpenOCD as the default debug interface. You can also use 387 a Segger J-Link with Segger's native tooling by overriding the runner, 388 appending ``--runner jlink`` to your ``west`` command(s). The J-Link should 389 be connected to the standard 2*5 pin debug connector (JH2) using an 390 appropriate adapter board and cable. 391 392Debugging 393========= 394 395Please refer to the `Flashing`_ section and run the ``west debug`` command 396instead of ``west flash``. 397 398References 399********** 400 401- `MAX32675EVKIT web page`_ 402 403.. _MAX32675EVKIT web page: 404 https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/max32675evkit.html 405
