1/*
2 * Copyright (c) 2024 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <adi/max32/max32672.dtsi>
10#include <adi/max32/max32672-pinctrl.dtsi>
11#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
12#include <zephyr/dt-bindings/input/input-event-codes.h>
13#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
14
15/ {
16	model = "Analog Devices MAX32672EVKIT";
17	compatible = "adi,max32672evkit";
18
19	chosen {
20		zephyr,console = &uart0;
21		zephyr,shell-uart = &uart0;
22		zephyr,sram = &sram3;
23		zephyr,flash = &flash0;
24		zephyr,display = &st7735;
25	};
26
27	leds {
28		compatible = "gpio-leds";
29		led1: led_1 {
30			gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
31			label = "Red LED";
32		};
33		led2: led_2 {
34			gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
35			label = "Green LED";
36		};
37	};
38
39	buttons {
40		compatible = "gpio-keys";
41		pb1: pb1 {
42			gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
43			label = "SW3";
44			zephyr,code = <INPUT_KEY_0>;
45		};
46	};
47
48	 /* These aliases are provided for compatibility with samples */
49	aliases {
50		led0 = &led1;
51		led1 = &led2;
52		sw0 = &pb1;
53		watchdog0 = &wdt0;
54	};
55
56	mipi_dbi {
57		compatible = "zephyr,mipi-dbi-spi";
58		/* Enable D/C line for 4wire mode */
59		/* dc-gpios = <&gpio0 19 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>; */
60		spi-dev = <&spi0>;
61		#address-cells = <1>;
62		#size-cells = <0>;
63
64		status = "okay";
65
66		st7735: st7735@0 {
67			compatible = "sitronix,st7735r";
68			mipi-max-frequency = <DT_FREQ_M(6)>;
69			mipi-mode = "MIPI_DBI_MODE_SPI_3WIRE";
70
71			reg = <0>;
72			width = <130>;
73			height = <132>;
74			x-offset = <0>;
75			y-offset = <0>;
76			madctl = <0xc0>;
77			colmod = <0x05>;
78			vmctr1 = <0x51>;
79			pwctr1 = [02 02];
80			pwctr2 = [c5];
81			pwctr3 = [0d 00];
82			pwctr4 = [8d 1a];
83			pwctr5 = [8d ee];
84			frmctr1 = [02 35 36];
85			frmctr2 = [02 35 36];
86			frmctr3 = [02 35 36 02 35 36];
87			gamctrp1 = [0a 1c 0c 14 33 2b 24 28 27 25 2c 39 00 05 03 0d];
88			gamctrn1 = [0a 1c 0c 14 33 2b 24 28 27 25 2d 3a 00 05 03 0d];
89		};
90	};
91};
92
93&uart0 {
94	pinctrl-0 = <&uart0a_tx_p0_9 &uart0a_rx_p0_8>;
95	pinctrl-names = "default";
96	current-speed = <115200>;
97	data-bits = <8>;
98	parity = "none";
99	status = "okay";
100};
101
102&clk_ipo {
103	status = "okay";
104};
105
106/*
107 * ERTCO is required for counter RTC
108 */
109&clk_ertco {
110	status = "okay";
111};
112
113&gpio0 {
114	status = "okay";
115};
116
117&gpio1 {
118	status = "okay";
119};
120
121&trng {
122	status = "okay";
123};
124
125&i2c0 {
126	status = "okay";
127	pinctrl-0 = <&i2c0a_scl_p0_6 &i2c0a_sda_p0_7>;
128	pinctrl-names = "default";
129};
130
131&dma0 {
132	status = "okay";
133};
134
135&wdt0 {
136	status = "okay";
137};
138
139&spi1 {
140	status = "okay";
141	pinctrl-0 = <&spi1a_mosi_p0_15 &spi1a_miso_p0_14 &spi1a_sck_p0_16 &spi1a_ss0_p0_17>;
142	pinctrl-names = "default";
143};
144
145&spi0a_mosi_p0_3 {
146	power-source=<MAX32_VSEL_VDDIOH>;
147};
148
149&spi0a_sck_p0_4 {
150	power-source=<MAX32_VSEL_VDDIOH>;
151};
152
153&spi0 {
154	status = "okay";
155	pinctrl-0 = <&spi0a_mosi_p0_3 &spi0a_miso_p0_2 &spi0a_sck_p0_4>;
156	pinctrl-names = "default";
157	cs-gpios = <&gpio0 5 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>;
158};
159
160&rtc_counter {
161	status = "okay";
162};
163