1/*
2 * Copyright (c) 2022 Nordic Semiconductor
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	uart0_default: uart0_default {
8		group1 {
9			psels = <NRF_PSEL(UART_TX, 0, 2)>,
10				<NRF_PSEL(UART_RX, 0, 5)>,
11				<NRF_PSEL(UART_CTS, 0, 14)>,
12				<NRF_PSEL(UART_RTS, 0, 18)>;
13		};
14	};
15
16	uart0_sleep: uart0_sleep {
17		group1 {
18			psels = <NRF_PSEL(UART_TX, 0, 2)>,
19				<NRF_PSEL(UART_RX, 0, 5)>,
20				<NRF_PSEL(UART_CTS, 0, 14)>,
21				<NRF_PSEL(UART_RTS, 0, 18)>;
22			low-power-enable;
23		};
24	};
25
26	i2c2_default: i2c2_default {
27		group1 {
28			psels = <NRF_PSEL(TWIM_SDA, 0, 10)>,
29				<NRF_PSEL(TWIM_SCL, 0, 11)>;
30		};
31	};
32
33	i2c2_sleep: i2c2_sleep {
34		group1 {
35			psels = <NRF_PSEL(TWIM_SDA, 0, 10)>,
36				<NRF_PSEL(TWIM_SCL, 0, 11)>;
37			low-power-enable;
38		};
39	};
40
41	spi3_default: spi3_default {
42		group1 {
43			psels = <NRF_PSEL(SPIM_SCK, 0, 6)>,
44				<NRF_PSEL(SPIM_MOSI, 0, 3)>,
45				<NRF_PSEL(SPIM_MISO, 0, 8)>;
46		};
47	};
48
49	spi3_sleep: spi3_sleep {
50		group1 {
51			psels = <NRF_PSEL(SPIM_SCK, 0, 6)>,
52				<NRF_PSEL(SPIM_MOSI, 0, 3)>,
53				<NRF_PSEL(SPIM_MISO, 0, 8)>;
54			low-power-enable;
55		};
56	};
57
58	pwm0_default: pwm0_default {
59		group1 {
60			psels = <NRF_PSEL(PWM_OUT0, 0, 21)>,
61				<NRF_PSEL(PWM_OUT1, 0, 22)>,
62				<NRF_PSEL(PWM_OUT2, 0, 25)>;
63			nordic,invert;
64		};
65	};
66
67	pwm0_sleep: pwm0_sleep {
68		group1 {
69			psels = <NRF_PSEL(PWM_OUT0, 0, 21)>,
70				<NRF_PSEL(PWM_OUT1, 0, 22)>,
71				<NRF_PSEL(PWM_OUT2, 0, 25)>;
72			low-power-enable;
73		};
74	};
75
76};
77