1 /*
2  * Copyright (c) 2018 Lexmark International, Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief Exception/interrupt context helpers for Cortex-A and Cortex-R CPUs
10  *
11  * Exception/interrupt context helpers.
12  */
13 
14 #ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_EXCEPTION_H_
15 #define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_EXCEPTION_H_
16 
17 #include <zephyr/arch/cpu.h>
18 
19 #ifdef _ASMLANGUAGE
20 
21 /* nothing */
22 
23 #else
24 
25 #include <zephyr/irq_offload.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
31 #ifdef CONFIG_IRQ_OFFLOAD
32 extern volatile irq_offload_routine_t offload_routine;
33 #endif
34 
35 /* Check the CPSR mode bits to see if we are in IRQ or FIQ mode */
arch_is_in_isr(void)36 static ALWAYS_INLINE bool arch_is_in_isr(void)
37 {
38 	return (arch_curr_cpu()->nested != 0U);
39 }
40 
arch_is_in_nested_exception(const struct arch_esf * esf)41 static ALWAYS_INLINE bool arch_is_in_nested_exception(const struct arch_esf *esf)
42 {
43 	return (arch_curr_cpu()->arch.exc_depth > 1U) ? (true) : (false);
44 }
45 
46 /**
47  * @brief No current implementation where core dump is not supported
48  *
49  * @param esf exception frame
50  * @param exc_return EXC_RETURN value present in LR after exception entry.
51  */
z_arm_set_fault_sp(const struct arch_esf * esf,uint32_t exc_return)52 static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_t exc_return)
53 {}
54 
55 #if defined(CONFIG_USERSPACE)
56 /*
57  * This function is used by privileged code to determine if the thread
58  * associated with the stack frame is in user mode.
59  */
z_arm_preempted_thread_in_user_mode(const struct arch_esf * esf)60 static ALWAYS_INLINE bool z_arm_preempted_thread_in_user_mode(const struct arch_esf *esf)
61 {
62 	return ((esf->basic.xpsr & CPSR_M_Msk) == CPSR_M_USR);
63 }
64 #endif
65 
66 #ifndef CONFIG_USE_SWITCH
67 extern void z_arm_cortex_r_svc(void);
68 #endif
69 
70 #ifdef __cplusplus
71 }
72 #endif
73 
74 #endif /* _ASMLANGUAGE */
75 
76 #endif /* ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_EXCEPTION_H_ */
77