1 /*
2  * Copyright (c) 2014 Wind River Systems, Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief ARM Cortex-M interrupt initialization
10  *
11  */
12 
13 #include <zephyr/arch/cpu.h>
14 #include <cmsis_core.h>
15 
16 /**
17  *
18  * @brief Initialize interrupts
19  *
20  * Ensures all interrupts have their priority set to _EXC_IRQ_DEFAULT_PRIO and
21  * not 0, which they have it set to when coming out of reset. This ensures that
22  * interrupt locking via BASEPRI works as expected.
23  *
24  */
25 
z_arm_interrupt_init(void)26 void z_arm_interrupt_init(void)
27 {
28 	int irq = 0;
29 
30 /* CONFIG_2ND_LVL_ISR_TBL_OFFSET could be treated as total number of level1 interrupts */
31 #if defined(CONFIG_MULTI_LEVEL_INTERRUPTS) && defined(CONFIG_2ND_LVL_ISR_TBL_OFFSET)
32 	for (; irq < CONFIG_2ND_LVL_ISR_TBL_OFFSET; irq++) {
33 #else
34 	for (; irq < CONFIG_NUM_IRQS; irq++) {
35 #endif
36 		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
37 	}
38 }
39