1 /*
2 * Copyright (c) 2013-2014 Wind River Systems, Inc.
3 * Copyright (c) 2020-2022 Qualcomm Innovation Center, Inc.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7 /**
8 * @file
9 * @brief Cache manipulation
10 *
11 * This module contains functions for manipulation caches.
12 */
13
14 #include <zephyr/arch/cpu.h>
15 #include <zephyr/cache.h>
16 #include <cmsis_core.h>
17
arch_dcache_enable(void)18 void arch_dcache_enable(void)
19 {
20 SCB_EnableDCache();
21 }
22
arch_dcache_disable(void)23 void arch_dcache_disable(void)
24 {
25 SCB_DisableDCache();
26 }
27
arch_dcache_flush_all(void)28 int arch_dcache_flush_all(void)
29 {
30 SCB_CleanDCache();
31
32 return 0;
33 }
34
arch_dcache_invd_all(void)35 int arch_dcache_invd_all(void)
36 {
37 SCB_InvalidateDCache();
38
39 return 0;
40 }
41
arch_dcache_flush_and_invd_all(void)42 int arch_dcache_flush_and_invd_all(void)
43 {
44 SCB_CleanInvalidateDCache();
45
46 return 0;
47 }
48
arch_dcache_flush_range(void * start_addr,size_t size)49 int arch_dcache_flush_range(void *start_addr, size_t size)
50 {
51 SCB_CleanDCache_by_Addr(start_addr, size);
52
53 return 0;
54 }
55
arch_dcache_invd_range(void * start_addr,size_t size)56 int arch_dcache_invd_range(void *start_addr, size_t size)
57 {
58 SCB_InvalidateDCache_by_Addr(start_addr, size);
59
60 return 0;
61 }
62
arch_dcache_flush_and_invd_range(void * start_addr,size_t size)63 int arch_dcache_flush_and_invd_range(void *start_addr, size_t size)
64 {
65 SCB_CleanInvalidateDCache_by_Addr(start_addr, size);
66
67 return 0;
68 }
69
arch_icache_enable(void)70 void arch_icache_enable(void)
71 {
72 SCB_EnableICache();
73 }
74
arch_icache_disable(void)75 void arch_icache_disable(void)
76 {
77 SCB_DisableICache();
78 }
79
arch_icache_flush_all(void)80 int arch_icache_flush_all(void)
81 {
82 return -ENOTSUP;
83 }
84
arch_icache_invd_all(void)85 int arch_icache_invd_all(void)
86 {
87 SCB_InvalidateICache();
88
89 return 0;
90 }
91
arch_icache_flush_and_invd_all(void)92 int arch_icache_flush_and_invd_all(void)
93 {
94 return -ENOTSUP;
95 }
96
arch_icache_flush_range(void * start_addr,size_t size)97 int arch_icache_flush_range(void *start_addr, size_t size)
98 {
99 return -ENOTSUP;
100 }
101
arch_icache_invd_range(void * start_addr,size_t size)102 int arch_icache_invd_range(void *start_addr, size_t size)
103 {
104 SCB_InvalidateICache_by_Addr(start_addr, size);
105
106 return 0;
107 }
108
arch_icache_flush_and_invd_range(void * start_addr,size_t size)109 int arch_icache_flush_and_invd_range(void *start_addr, size_t size)
110 {
111 return -ENOTSUP;
112 }
113
arch_cache_init(void)114 void arch_cache_init(void)
115 {
116 }
117
