1 /*
2 * Copyright (c) 2023 Andriy Gelman <andriy.gelman@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <zephyr/sys/printk.h>
9 #include <zephyr/device.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/ztest.h>
13
14 #define NODELABEL DT_NODELABEL(samplenode)
15 static const struct device *clk_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(NODELABEL));
16
pwm_clock_setup(void)17 static void *pwm_clock_setup(void)
18 {
19 int ret;
20 uint32_t clock_rate;
21 uint32_t clock_rate_dt = DT_PROP_BY_PHANDLE(NODELABEL, clocks, clock_frequency);
22
23 zassert_equal(device_is_ready(clk_dev), true, "%s: PWM clock device is not ready",
24 clk_dev->name);
25
26 ret = clock_control_get_rate(clk_dev, 0, &clock_rate);
27 zassert_equal(0, ret, "%s: Unexpected err (%d) from clock_control_get_rate",
28 clk_dev->name, ret);
29
30 zassert_equal(clock_rate_dt, clock_rate,
31 "%s: devicetree clock rate mismatch. Expected %dHz Fetched %dHz",
32 clk_dev->name, clock_rate_dt, clock_rate);
33
34 ret = clock_control_on(clk_dev, 0);
35 zassert_equal(0, ret, "%s: Unexpected err (%d) from clock_control_on", clk_dev->name, ret);
36
37 return NULL;
38 }
39
ZTEST(pwm_clock,test_clock_control_get_rate)40 ZTEST(pwm_clock, test_clock_control_get_rate)
41 {
42 int ret;
43 uint32_t clock_rate;
44
45 ret = clock_control_get_rate(clk_dev, 0, &clock_rate);
46 zassert_equal(0, ret, "%s: Unexpected err (%d) from clock_control_get_rate",
47 clk_dev->name, ret);
48 }
49
ZTEST(pwm_clock,test_clock_control_set_rate)50 ZTEST(pwm_clock, test_clock_control_set_rate)
51 {
52 int ret;
53 uint32_t clock_rate, clock_rate_new;
54
55 ret = clock_control_get_rate(clk_dev, 0, &clock_rate);
56 zassert_equal(0, ret, "%s: Unexpected err (%d) from clock_control_get_rate",
57 clk_dev->name, ret);
58
59 clock_rate /= 2;
60
61 ret = clock_control_set_rate(clk_dev, 0, (clock_control_subsys_rate_t)clock_rate);
62 zassert_equal(0, ret, "%s: unexpected err (%d) from clock_control_set_rate",
63 clk_dev->name, ret);
64
65 ret = clock_control_get_rate(clk_dev, 0, &clock_rate_new);
66 zassert_equal(0, ret, "%s: Unexpected err (%d) from clock_control_get_rate",
67 clk_dev->name, ret);
68
69 zassert_equal(clock_rate, clock_rate_new,
70 "%s: Clock rate mismatch. Expected %dHz Fetched %dHz", clk_dev->name,
71 clock_rate, clock_rate_new);
72 }
73
74 ZTEST_SUITE(pwm_clock, NULL, pwm_clock_setup, NULL, NULL, NULL);
75
