1# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
2# SPDX-License-Identifier: Apache-2.0
3
4if SOC_ARC_HSDK4XD
5
6config CPU_HS4X
7	default y
8
9config NUM_IRQ_PRIO_LEVELS
10	# This processor supports 2 priority levels:
11	# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
12	default 2
13
14config NUM_IRQS
15	# must be > the highest interrupt number used
16	default 88
17
18config RGF_NUM_BANKS
19	# Actually cpu has 4 banks but zephys currently supports up to 2
20	default 2
21
22config SYS_CLOCK_HW_CYCLES_PER_SEC
23	default 500000000
24
25config ARC_FIRQ
26	default y
27
28config CODE_DENSITY
29	default y
30
31config ARCV2_TIMER_IRQ_PRIORITY
32	default 1
33
34config ARC_CONNECT
35	default y
36
37config MP_MAX_NUM_CPUS
38	default 4
39
40config UART_NS16550_ACCESS_WORD_ONLY
41	default y
42	depends on UART_NS16550
43
44config ARC_HAS_ACCL_REGS
45	default y
46
47config ARC_EARLY_SOC_INIT
48	default y
49
50config ARC_HAS_STACK_CHECKING
51	default n
52
53endif # SOC_ARC_HS4XD
54