1 /*
2  * Copyright (c) 2021 Katsuhiro Suzuki
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/init.h>
8 #include <zephyr/devicetree.h>
9 #include <zephyr/sys/util.h>
10 #include "prci.h"
11 
12 BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
13 	"Unsupported CORECLK frequency");
14 BUILD_ASSERT(DT_PROP(DT_NODELABEL(tlclk), clock_div) == 2,
15 	"Unsupported TLCLK divider");
16 
17 /*
18  * Switch the clock source to 1GHz PLL from 33.333MHz oscillator on the HiFive
19  * Unleashed board.
20  */
fu540_clock_init(void)21 static int fu540_clock_init(void)
22 {
23 
24 	PRCI_REG(PRCI_COREPLLCFG0) =
25 		PLL_R(0) |   /* input divider: Fin / (0 + 1) = 33.33MHz */
26 		PLL_F(59) |  /* VCO: 2 x (59 + 1) = 120 = 3999.6MHz */
27 		PLL_Q(2) |   /* output divider: VCO / 2^2 = 999.9MHz */
28 		PLL_RANGE(PLL_RANGE_33MHZ) |
29 		PLL_BYPASS(PLL_BYPASS_DISABLE) |
30 		PLL_FSE(PLL_FSE_INTERNAL);
31 	while ((PRCI_REG(PRCI_COREPLLCFG0) & PLL_LOCK(1)) == 0)
32 		;
33 
34 	/* Switch clock to COREPLL */
35 	PRCI_REG(PRCI_CORECLKSEL) = CORECLKSEL_CORECLKSEL(CORECLKSEL_CORE_PLL);
36 
37 	return 0;
38 }
39 
40 SYS_INIT(fu540_clock_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
41