1 /*
2 * Copyright (c) 2023 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/init.h>
8 #include <stdint.h>
9 #include <zephyr/drivers/syscon.h>
10 #include "soc.h"
11 #include <zephyr/sys/util_macro.h>
12
13 static const struct device *const prcrn_dev = DEVICE_DT_GET(DT_NODELABEL(prcrn));
14 static const struct device *const prcrs_dev = DEVICE_DT_GET(DT_NODELABEL(prcrs));
15 static const struct device *const sckcr_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr));
16 static const struct device *const sckcr2_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr2));
17
rzt2m_unlock_prcrn(uint32_t mask)18 void rzt2m_unlock_prcrn(uint32_t mask)
19 {
20 uint32_t prcrn;
21
22 syscon_read_reg(prcrn_dev, 0, &prcrn);
23 prcrn |= PRC_KEY_CODE | mask;
24
25 syscon_write_reg(prcrn_dev, 0, prcrn);
26 }
27
rzt2m_lock_prcrn(uint32_t mask)28 void rzt2m_lock_prcrn(uint32_t mask)
29 {
30 uint32_t prcrn;
31
32 syscon_read_reg(prcrn_dev, 0, &prcrn);
33 prcrn &= ~mask;
34 prcrn |= PRC_KEY_CODE;
35
36 syscon_write_reg(prcrn_dev, 0, prcrn);
37 }
38
rzt2m_unlock_prcrs(uint32_t mask)39 void rzt2m_unlock_prcrs(uint32_t mask)
40 {
41 uint32_t prcrs;
42
43 syscon_read_reg(prcrs_dev, 0, &prcrs);
44 prcrs |= PRC_KEY_CODE | mask;
45
46 syscon_write_reg(prcrs_dev, 0, prcrs);
47 }
48
rzt2m_lock_prcrs(uint32_t mask)49 void rzt2m_lock_prcrs(uint32_t mask)
50 {
51 uint32_t prcrs;
52
53 syscon_read_reg(prcrs_dev, 0, &prcrs);
54 prcrs &= ~mask;
55 prcrs |= PRC_KEY_CODE;
56
57 syscon_write_reg(prcrs_dev, 0, prcrs);
58 }
59
rzt2m_set_sckcr2(uint32_t mask)60 void rzt2m_set_sckcr2(uint32_t mask)
61 {
62 syscon_write_reg(sckcr2_dev, 0, mask);
63 }
64
rzt2m_get_sckcr2(void)65 uint32_t rzt2m_get_sckcr2(void)
66 {
67 uint32_t reg;
68
69 syscon_read_reg(sckcr2_dev, 0, ®);
70 return reg;
71 }
72
rzt2m_set_sckcr(uint32_t mask)73 void rzt2m_set_sckcr(uint32_t mask)
74 {
75 syscon_write_reg(sckcr_dev, 0, mask);
76 }
77
rzt2m_get_sckcr(void)78 uint32_t rzt2m_get_sckcr(void)
79 {
80 uint32_t reg;
81
82 syscon_read_reg(sckcr_dev, 0, ®);
83 return reg;
84 }
85
rzt2m_enable_counters(void)86 void rzt2m_enable_counters(void)
87 {
88 const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(gsc));
89
90 syscon_write_reg(dev, 0, CNTCR_EN);
91 }
92
rzt2m_init(void)93 static int rzt2m_init(void)
94 {
95 /* Unlock the Protect Registers
96 * so that device drivers can access configuration registers of peripherals.
97 */
98 /* After the device drivers are done, lock the Protect Registers. */
99 rzt2m_unlock_prcrs(PRCRS_GPIO | PRCRS_CLK);
100 rzt2m_unlock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0);
101
102 /* Reset the System Clock Control Registers to default values */
103 rzt2m_set_sckcr(
104 CLMASEL |
105 PHYSEL |
106 FSELCANFD |
107 FSELXSPI0_DEFAULT |
108 FSELXSPI1_DEFAULT |
109 CKIO_DEFAULT
110 );
111
112 rzt2m_set_sckcr2(FSELCPU0_DEFAULT | FSELCPU1_DEFAULT);
113
114 rzt2m_lock_prcrs(PRCRS_GPIO | PRCRS_CLK);
115 rzt2m_lock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0);
116
117 rzt2m_enable_counters();
118 return 0;
119 }
120
121 SYS_INIT(rzt2m_init, PRE_KERNEL_1, 0);
122
