1 /*
2  * Copyright (c) 2021 NXP
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <string.h>
8 #include <errno.h>
9 
10 #include <zephyr/sys/sys_io.h>
11 
12 #include <adsp/cache.h>
13 
14 #ifndef __INC_IMX_SOC_H
15 #define __INC_IMX_SOC_H
16 
17 /* Macros related to interrupt handling */
18 #define XTENSA_IRQ_NUM_SHIFT			0
19 #define XTENSA_IRQ_NUM_MASK			0xff
20 
21 /*
22  * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
23  *
24  * 1. Peripheral Register bit offset.
25  */
26 #define XTENSA_IRQ_NUMBER(_irq) \
27 	((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
28 
29 extern void z_soc_irq_enable(uint32_t irq);
30 extern void z_soc_irq_disable(uint32_t irq);
31 extern int z_soc_irq_is_enabled(unsigned int irq);
32 
33 #endif /* __INC_IMX_SOC_H */
34