1# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
2# SPDX-License-Identifier: Apache-2.0
3
4config SOC_NEORV32
5	select RISCV
6	select RISCV_ISA_RV32I
7	select RISCV_ISA_EXT_M
8	select RISCV_ISA_EXT_A
9	select RISCV_ISA_EXT_ZICSR
10	select RISCV_ISA_EXT_ZIFENCEI
11	select RISCV_PRIVILEGED
12
13if SOC_NEORV32
14
15config SOC_NEORV32_V1_8_6
16	bool "v1.8.6"
17	# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
18	select ATOMIC_OPERATIONS_C
19
20config SOC_NEORV32_VERSION
21	hex
22	default 0x01080600 if SOC_NEORV32_V1_8_6
23	help
24	  The targeted NEORV32 version as BCD-coded number. The format is
25	  identical to that of the NEORV32 Machine implementation ID (mimpid)
26	  register.
27
28config SOC_NEORV32_ISA_C
29	bool "RISC-V ISA Extension \"C\""
30	select RISCV_ISA_EXT_C
31	help
32	  Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
33	  "C" extension (Compressed Instructions).
34
35endif # SOC_NEORV32
36