1 /* 2 * Copyright (c) 2020 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file Header containing definitions for MCHP eSPI SAF 9 */ 10 11 #ifndef _SOC_ESPI_SAF_H_ 12 #define _SOC_ESPI_SAF_H_ 13 14 #include <stdint.h> 15 #include <zephyr/sys/util.h> 16 #include <soc.h> 17 18 #define MCHP_SAF_MAX_FLASH_DEVICES 2U 19 20 /* 21 * SAF hardware state machine timings 22 * poll timeout is in 32KHz clock periods 23 * poll interval is in AHB clock(48MHz) units. 24 * suspend resume interval is in 32KHz clock periods. 25 * consecutive read timeout is in AHB clock periods. 26 * suspend check delay is in AHB clock(48MHz) periods. 27 */ 28 #define MCHP_SAF_FLASH_POLL_TIMEOUT 0x28000U 29 #define MCHP_SAF_FLASH_POLL_INTERVAL 0U 30 #define MCHP_SAF_FLASH_SUS_RSM_INTERVAL 8U 31 #define MCHP_SAF_FLASH_CONSEC_READ_TIMEOUT 2U 32 #define MCHP_SAF_FLASH_SUS_CHK_DELAY 0U 33 34 /* Default SAF Map of eSPI TAG numbers to master numbers */ 35 #define MCHP_SAF_TAG_MAP0_DFLT 0x23221100 36 #define MCHP_SAF_TAG_MAP1_DFLT 0x77677767 37 #define MCHP_SAF_TAG_MAP2_DFLT 0x00000005 38 39 /* 40 * Default QMSPI clock divider and chip select timing. 41 * QMSPI master clock is 48MHz AHB clock. 42 */ 43 #define MCHP_SAF_QMSPI_CLK_DIV 2U 44 #define MCHP_SAF_QMSPI_CS_TIMING 0x03000101U 45 46 /* SAF QMSPI programming */ 47 48 #define MCHP_SAF_QMSPI_NUM_FLASH_DESCR 6U 49 #define MCHP_SAF_QMSPI_CS0_START_DESCR 0U 50 #define MCHP_SAF_QMSPI_CS1_START_DESCR \ 51 (MCHP_SAF_QMSPI_CS0_START_DESCR + MCHP_SAF_QMSPI_NUM_FLASH_DESCR) 52 53 /* SAF engine requires start indices of descriptor chains */ 54 #define MCHP_SAF_CM_EXIT_START_DESCR 12U 55 #define MCHP_SAF_CM_EXIT_LAST_DESCR 13U 56 #define MCHP_SAF_POLL_STS_START_DESCR 14U 57 #define MCHP_SAF_POLL_STS_END_DESCR 15U 58 #define MCHP_SAF_NUM_GENERIC_DESCR 4U 59 60 /* QMSPI descriptors 12-15 for all SPI flash devices */ 61 /* #define SAF_QMSPI_DESCR12 0x0002D40E */ 62 63 /* 64 * QMSPI descriptors 12-13 are exit continuous mode 65 */ 66 #define MCHP_SAF_EXIT_CM_DESCR12 \ 67 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_ONES | \ 68 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 69 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 70 MCHP_QMSPI_C_XFR_UNITS_1 | \ 71 MCHP_QMSPI_C_NEXT_DESCR(13) | \ 72 MCHP_QMSPI_C_XFR_NUNITS(1)) 73 74 #define MCHP_SAF_EXIT_CM_DESCR13 \ 75 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 76 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 77 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 78 MCHP_QMSPI_C_XFR_UNITS_1 | \ 79 MCHP_QMSPI_C_NEXT_DESCR(0) | \ 80 MCHP_QMSPI_C_XFR_NUNITS(9) | \ 81 MCHP_QMSPI_C_DESCR_LAST) 82 83 /* 84 * QMSPI descriptors 14-15 are poll 16-bit flash status 85 * Transmit one byte opcode at 1X (no DMA). 86 * Receive two bytes at 1X (no DMA). 87 */ 88 #define MCHP_SAF_POLL_DESCR14 \ 89 (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \ 90 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 91 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 92 MCHP_QMSPI_C_XFR_UNITS_1 | \ 93 MCHP_QMSPI_C_NEXT_DESCR(15) | \ 94 MCHP_QMSPI_C_XFR_NUNITS(1)) 95 96 #define MCHP_SAF_POLL_DESCR15 \ 97 (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DIS | \ 98 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 99 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 100 MCHP_QMSPI_C_XFR_UNITS_1 | \ 101 MCHP_QMSPI_C_NEXT_DESCR(0) | \ 102 MCHP_QMSPI_C_XFR_NUNITS(2) | \ 103 MCHP_QMSPI_C_DESCR_LAST) 104 105 106 /* SAF Pre-fetch optimization mode */ 107 #define MCHP_SAF_PREFETCH_MODE MCHP_SAF_FL_CFG_MISC_PFOE_DFLT 108 109 #define MCHP_SAF_CFG_MISC_PREFETCH_EXPEDITED 0x03U 110 111 /* 112 * SAF Opcode 32-bit register value. 113 * Each byte contain a SPI flash 8-bit opcode. 114 * NOTE1: opcode value of 0 = flash does not support this operation 115 * NOTE2: 116 * SAF Opcode A 117 * op0 = SPI flash write-enable opcode 118 * op1 = SPI flash program/erase suspend opcode 119 * op2 = SPI flash program/erase resume opcode 120 * op3 = SPI flash read STATUS1 opcode 121 * SAF Opcode B 122 * op0 = SPI flash erase 4KB sector opcode 123 * op1 = SPI flash erase 32KB sector opcode 124 * op2 = SPI flash erase 64KB sector opcode 125 * op3 = SPI flash page program opcode 126 * SAF Opcode C 127 * op0 = SPI flash read 1-4-4 continuous mode opcode 128 * op1 = SPI flash op0 mode byte value for non-continuous mode 129 * op2 = SPI flash op0 mode byte value for continuous mode 130 * op3 = SPI flash read STATUS2 opcode 131 */ 132 #define MCHP_SAF_OPCODE_REG_VAL(op0, op1, op2, op3) \ 133 (((uint32_t)(op0)&0xffU) | (((uint32_t)(op1)&0xffU) << 8) | \ 134 (((uint32_t)(op2)&0xffU) << 16) | (((uint32_t)(op3)&0xffU) << 24)) 135 136 /* 137 * SAF Flash Config CS0/CS1 QMSPI descriptor indices register value 138 * e = First QMSPI descriptor index for enter continuous mode chain 139 * r = First QMSPI descriptor index for continuous mode read chain 140 * s = Index of QMSPI descriptor in continuous mode read chain that 141 * contains the data length field. 142 */ 143 #define MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(e, r, s) (((uint32_t)(e)&0xfU) | \ 144 (((uint32_t)(r)&0xfU) << 8) | (((uint32_t)(s)&0xfU) << 12)) 145 146 /* W25Q128 SPI flash device connected size in bytes */ 147 #define MCHP_W25Q128_SIZE (16U * 1024U * 1024U) 148 149 /* 150 * Six QMSPI descriptors describe SPI flash opcode protocols. 151 * Example: W25Q128 152 */ 153 /* Continuous mode read: transmit-quad 24-bit address and mode byte */ 154 #define MCHP_W25Q128_CM_RD_D0 \ 155 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \ 156 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 157 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 158 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4)) 159 160 /* Continuous mode read: transmit-quad 4 dummy clocks with I/O tri-stated */ 161 #define MCHP_W25Q128_CM_RD_D1 \ 162 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 163 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 164 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 165 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2)) 166 167 /* Continuous mode read: read N bytes */ 168 #define MCHP_W25Q128_CM_RD_D2 \ 169 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 170 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 171 MCHP_QMSPI_C_RX_DMA_4B | MCHP_QMSPI_C_CLOSE | \ 172 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(0) | \ 173 MCHP_QMSPI_C_DESCR_LAST) 174 175 /* Enter Continuous mode: transmit-single CM quad read opcode */ 176 #define MCHP_W25Q128_ENTER_CM_D0 \ 177 (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \ 178 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 179 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 180 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1)) 181 182 /* Enter Continuous mode: transmit-quad 24-bit address and mode byte */ 183 #define MCHP_W25Q128_ENTER_CM_D1 \ 184 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \ 185 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 186 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 187 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(4)) 188 189 /* Enter Continuous mode: read-quad 3 bytes */ 190 #define MCHP_W25Q128_ENTER_CM_D2 \ 191 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 192 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 193 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 194 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(3) | \ 195 MCHP_QMSPI_C_DESCR_LAST) 196 197 #define MCHP_W25Q128_OPA MCHP_SAF_OPCODE_REG_VAL(0x06U, 0x75U, 0x7aU, 0x05U) 198 #define MCHP_W25Q128_OPB MCHP_SAF_OPCODE_REG_VAL(0x20U, 0x52U, 0xd8U, 0x02U) 199 #define MCHP_W25Q128_OPC MCHP_SAF_OPCODE_REG_VAL(0xebU, 0xffU, 0xa5U, 0x35U) 200 201 /* W25Q128 STATUS2 bit[7] == 0 part is NOT in suspend state */ 202 #define MCHP_W25Q128_POLL2_MASK 0xff7fU 203 204 /* 205 * SAF Flash Continuous Mode Prefix register value 206 * b[7:0] = continuous mode prefix opcode 207 * b[15:8] = continuous mode prefix opcode data 208 * Some SPI flash devices require a prefix command before 209 * they will enter continuous mode. 210 * A zero value means the SPI flash does not require a prefix 211 * command. 212 */ 213 #define MCHP_W25Q128_CONT_MODE_PREFIX_VAL 0U 214 215 #define MCHP_W25Q128_FLAGS 0U 216 217 218 /* W25Q256 SPI flash device connected size in bytes */ 219 #define MCHP_W25Q256_SIZE (32U * 1024U * 1024U) 220 221 /* 222 * Six QMSPI descriptors describe SPI flash opcode protocols. 223 * W25Q256 device. 224 */ 225 226 /* Continuous Mode Read: Transmit-quad opcode plus 32-bit address */ 227 #define MCHP_W25Q256_CM_RD_D0 \ 228 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \ 229 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 230 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 231 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5)) 232 233 #define MCHP_W25Q256_CM_RD_D1 \ 234 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 235 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 236 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 237 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(2)) 238 239 #define MCHP_W25Q256_CM_RD_D2 \ 240 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 241 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_EN | \ 242 MCHP_QMSPI_C_RX_DMA_4B | MCHP_QMSPI_C_CLOSE | \ 243 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(0) | \ 244 MCHP_QMSPI_C_DESCR_LAST) 245 246 /* Enter Continuous mode: transmit-single CM quad read opcode */ 247 #define MCHP_W25Q256_ENTER_CM_D0 \ 248 (MCHP_QMSPI_C_IFM_1X | MCHP_QMSPI_C_TX_DATA | \ 249 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 250 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 251 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(1)) 252 253 /* Enter Continuous mode: transmit-quad 32-bit address and mode byte */ 254 #define MCHP_W25Q256_ENTER_CM_D1 \ 255 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DATA | \ 256 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 257 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_NO_CLOSE | \ 258 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(5)) 259 260 /* Enter Continuous mode: read-quad 3 bytes */ 261 #define MCHP_W25Q256_ENTER_CM_D2 \ 262 (MCHP_QMSPI_C_IFM_4X | MCHP_QMSPI_C_TX_DIS | \ 263 MCHP_QMSPI_C_TX_DMA_DIS | MCHP_QMSPI_C_RX_DIS | \ 264 MCHP_QMSPI_C_RX_DMA_DIS | MCHP_QMSPI_C_CLOSE | \ 265 MCHP_QMSPI_C_XFR_UNITS_1 | MCHP_QMSPI_C_XFR_NUNITS(3) | \ 266 MCHP_QMSPI_C_DESCR_LAST) 267 268 #define MCHP_W25Q256_OPA MCHP_SAF_OPCODE_REG_VAL(0x06U, 0x75U, 0x7aU, 0x05U) 269 #define MCHP_W25Q256_OPB MCHP_SAF_OPCODE_REG_VAL(0x20U, 0x52U, 0xd8U, 0x02U) 270 #define MCHP_W25Q256_OPC MCHP_SAF_OPCODE_REG_VAL(0xebU, 0xffU, 0xa5U, 0x35U) 271 272 #define MCHP_W25Q256_POLL2_MASK 0xff7fU 273 274 #define MCHP_W25Q256_CONT_MODE_PREFIX_VAL 0U 275 276 #define MCHP_W25Q256_FLAGS 0U 277 278 /* SAF Flash Config CS0 QMSPI descriptor indices */ 279 #define MCHP_CS0_CFG_DESCR_IDX_REG_VAL \ 280 MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(3U, 0U, 2U) 281 282 /* SAF Flash Config CS1 QMSPI descriptor indices */ 283 #define MCHP_CS1_CFG_DESCR_IDX_REG_VAL \ 284 MCHP_SAF_CS_CFG_DESCR_IDX_REG_VAL(9U, 6U, 8U) 285 286 #define MCHP_SAF_HW_CFG_FLAG_FREQ 0x01U 287 #define MCHP_SAF_HW_CFG_FLAG_CSTM 0x02U 288 #define MCHP_SAF_HW_CFG_FLAG_CPHA 0x04U 289 290 /* enable SAF prefetch */ 291 #define MCHP_SAF_HW_CFG_FLAG_PFEN 0x10U 292 /* Use expedited prefetch instead of default */ 293 #define MCHP_SAF_HW_CFG_FLAG_PFEXP 0x20U 294 295 /* 296 * Override the default tag map value when this bit is set 297 * in a tag_map[]. 298 */ 299 #define MCHP_SAF_HW_CFG_TAGMAP_USE BIT(31) 300 301 struct espi_saf_hw_cfg { 302 uint32_t qmspi_freq_hz; 303 uint32_t qmspi_cs_timing; 304 uint8_t qmspi_cpha; 305 uint8_t flags; 306 uint32_t generic_descr[MCHP_SAF_NUM_GENERIC_DESCR]; 307 uint32_t tag_map[MCHP_ESPI_SAF_TAGMAP_MAX]; 308 }; 309 310 /* 311 * SAF local flash configuration. 312 * SPI flash device size in bytes 313 * SPI opcodes for SAF Opcode A register 314 * SPI opcodes for SAF Opcode B register 315 * SPI opcodes for SAF Opcode C register 316 * QMSPI descriptors describing SPI opcode transmit and 317 * data read. 318 * SAF controller Poll2 Mast value specific for this flash device 319 * SAF continuous mode prefix register value for those flashes requiring 320 * a prefix byte transmitted before the enter continuous mode command. 321 * Start QMSPI descriptor numbers. 322 * miscellaneous flags. 323 */ 324 325 /* Flags */ 326 #define MCHP_FLASH_FLAG_ADDR32 BIT(0) 327 328 struct espi_saf_flash_cfg { 329 uint32_t flashsz; 330 uint32_t opa; 331 uint32_t opb; 332 uint32_t opc; 333 uint16_t poll2_mask; 334 uint16_t cont_prefix; 335 uint16_t cs_cfg_descr_ids; 336 uint16_t flags; 337 uint32_t descr[MCHP_SAF_QMSPI_NUM_FLASH_DESCR]; 338 }; 339 340 341 /* 342 * 17 flash protection regions 343 * Each region is described by: 344 * SPI start address. 20-bits = bits[31:12] of SPI address 345 * SPI limit address. 20-bits = bits[31:12] of last SPI address 346 * 8-bit bit map of eSPI master write-erase permission 347 * 8-bit bit map of eSPI master read permission 348 * eSPI master numbers 0 - 7 correspond to bits 0 - 7. 349 * 350 * Protection region lock: 351 * One 32-bit register with bits[16:0] -> protection regions 16:0 352 * 353 * eSPI Host maps threads by a tag number to master numbers. 354 * Thread numbers are 4-bit 355 * Master numbers are 3-bit 356 * Master number Thread numbers Description 357 * 0 0h, 1h Host PCH HW init 358 * 1 2h, 3h Host CPU access(HW/BIOS/SMM/SW) 359 * 2 4h, 5h Host PCH ME 360 * 3 6h Host PCH LAN 361 * 4 N/A Not defined/used 362 * 5 N/A EC Firmware portal access 363 * 6 9h, Dh Host PCH IE 364 * 7 N/A Not defined/used 365 * 366 * NOTE: eSPI SAF specification allows master 0 (Host PCH HW) full 367 * access to all protection regions. 368 * 369 * SAF TAG Map registers 0 - 2 map eSPI TAG values 0h - Fh to 370 * the three bit master number. Each 32-bit register contains 3-bit 371 * fields aligned on nibble boundaries holding the master number 372 * associated with the eSPI tag (thread) number. 373 * A master value of 7h in a field indicates a non-existent map entry. 374 * 375 * bit map of registers to program 376 * b[2:0] = TAG Map[2:0] 377 * b[20:4] = ProtectionRegions[16:0] 378 * bit map of PR's to lock 379 * b[20:4] = ProtectionRegions[16:0] 380 * 381 */ 382 #define MCHP_SAF_PR_FLAG_ENABLE 0x01U 383 #define MCHP_SAF_PR_FLAG_LOCK 0x02U 384 385 #define MCHP_SAF_MSTR_HOST_PCH 0U 386 #define MCHP_SAF_MSTR_HOST_CPU 1U 387 #define MCHP_SAF_MSTR_HOST_PCH_ME 2U 388 #define MCHP_SAF_MSTR_HOST_PCH_LAN 3U 389 #define MCHP_SAF_MSTR_RSVD4 4U 390 #define MCHP_SAF_MSTR_EC 5U 391 #define MCHP_SAF_MSTR_HOST_PCH_IE 6U 392 393 struct espi_saf_pr { 394 uint32_t start; 395 uint32_t size; 396 uint8_t master_bm_we; 397 uint8_t master_bm_rd; 398 uint8_t pr_num; 399 uint8_t flags; /* bit[0]==1 is lock the region */ 400 }; 401 402 struct espi_saf_protection { 403 size_t nregions; 404 const struct espi_saf_pr *pregions; 405 }; 406 407 #endif /* _SOC_ESPI_SAF_H_ */ 408
