1 /* 2 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MEC_GLOBAL_CFG_H 8 #define _MEC_GLOBAL_CFG_H 9 10 #include <stdint.h> 11 #include <stddef.h> 12 13 /* 14 * Device and Revision ID 32-bit register 15 * b[7:0] = Revision 16 * b[15:8] = Device Sub-ID 17 * b[31:16] = Device ID 18 * This register can be accesses as bytes or a single 32-bit read from 19 * the EC. Host access byte access via the Host visible configuration 20 * register space at 0x2E/0x2F (default). 21 */ 22 #define MCHP_GCFG_DEV_ID_REG32_OFS 28u 23 #define MCHP_GCFG_DEV_ID_REG_MASK GENMASK(31, 0) 24 #define MCHP_GCFG_REV_ID_POS 0 25 #define MCHP_GCFG_DID_REV_MASK GENMASK(7, 0) 26 #define MCHP_GCFG_DID_SUB_ID_POS 8 27 #define MCHP_GCFG_DID_SUB_ID_MASK GENMASK(15, 8) 28 #define MCHP_GCFG_DID_DEV_ID_POS 16 29 #define MCHP_GCFG_DID_DEV_ID_MASK GENMASK(31, 16) 30 31 /* Byte[0] at offset 0x1c is the 8-bit revision ID */ 32 #define MCHP_GCFG_REV_A1 2u 33 #define MCHP_GCFG_REV_B0 3u 34 35 /* 36 * Byte[1] at offset 0x1D is the 8-bit Sub-ID 37 * bits[3:0] = package type 38 * bits[7:4] = chip family 39 */ 40 #define MCHP_GCFG_SUB_ID_OFS 0x1du 41 #define MCHP_GCFG_SUB_ID_PKG_POS 0 42 #define MCHP_GCFG_SUB_ID_PKG_MASK GENMASK(3, 0) 43 #define MCHP_GCFG_SUB_ID_PKG_UNDEF 0u 44 #define MCHP_GCFG_SUB_ID_PKG_64_PIN 1u 45 #define MCHP_GCFG_SUB_ID_PKG_84_PIN 2u 46 #define MCHP_GCFG_SUB_ID_PKG_128_PIN 3u 47 #define MCHP_GCFG_SUB_ID_PKG_144_PIN 4u 48 #define MCHP_GCFG_SUB_ID_PKG_176_PIN 7u 49 /* chip family field */ 50 #define MCHP_GCFG_SUB_ID_FAM_POS 4u 51 #define MCHP_GCFG_SUB_ID_FAM_MASK GENMASK(7, 4) 52 #define MCHP_GCFG_SUB_ID_FAM_UNDEF 0u 53 #define MCHP_GCFG_SUB_ID_FAM_1 0x10u 54 #define MCHP_GCFG_SUB_ID_FAM_2 0x20u 55 #define MCHP_GCFG_SUB_ID_FAM_3 0x30u 56 #define MCHP_GCFG_SUB_ID_FAM_4 0x40u 57 #define MCHP_GCFG_SUB_ID_FAM_5 0x50u 58 #define MCHP_GCFG_SUB_ID_FAM_6 0x60u 59 #define MCHP_GCFG_SUB_ID_FAM_7 0x70u 60 61 #define MCHP_GCFG_DEV_ID_LSB_OFS 0x1eu 62 #define MCHP_GCFG_DEV_ID_MSB_OFS 0x1fu 63 #define MCHP_GCFG_DEV_ID_172X 0x0022u 64 #define MCHP_GCFG_DEV_ID_172X_LSB 0x22u 65 #define MCHP_GCFG_DEV_ID_172X_MSB 0x00u 66 67 /* SZ 144-pin package parts */ 68 #define MCHP_GCFG_DEVID_1723_144 0x00223400u 69 #define MCHP_GCFG_DEVID_1727_144 0x00227400u 70 /* LJ 176-pin package parts */ 71 #define MCHP_GCFG_DID_1721_176 0x00222700u 72 #define MCHP_GCFG_DID_1723_176 0x00223700u 73 #define MCHP_GCFG_DID_1727_176 0x00227700u 74 75 /* Legacy Device ID value */ 76 #define MCHP_CCFG_LEGACY_DID_REG_OFS 0x20u 77 #define MCHP_GCFG_LEGACY_DEV_ID 0xfeu 78 79 /* Host access via configuration port (default I/O locations 0x2E/0x2F) */ 80 #define MCHP_HOST_CFG_INDEX_IO_DFLT 0x2eu 81 #define MCHP_HOST_CFG_DATA_IO_DFLT 0x2fu 82 #define MCHP_HOST_CFG_UNLOCK 0x55u 83 #define MCHP_HOST_CFG_LOCK 0xaau 84 /* Logical Device Configuration Indices */ 85 #define MCHP_HOST_CFG_LDN_IDX 7u 86 #define MCHP_HOST_CFG_LD_ACTIVATE_IDX 0x30u 87 #define MCHP_HOST_CFG_LD_BASE_ADDR_IDX 0x34u 88 #define MCHP_HOST_CFG_LD_CFG_SEL_IDX 0xf0u 89 90 /* Global Configuration Registers */ 91 struct global_cfg_regs { 92 volatile uint8_t RSVD0[2]; 93 volatile uint8_t TEST02; 94 volatile uint8_t RSVD1[4]; 95 volatile uint8_t LOG_DEV_NUM; 96 volatile uint8_t RSVD2[20]; 97 volatile uint32_t DEV_REV_ID; 98 volatile uint8_t LEGACY_DEV_ID; 99 volatile uint8_t RSVD3[14]; 100 }; 101 102 #endif /* #ifndef _MEC_GLOBAL_CFG_H */ 103
