1 /*
2  * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /**
8  * @file
9  * @brief interrupt management code for riscv SOCs supporting the riscv
10 	  privileged architecture specification
11  */
12 #include <zephyr/irq.h>
13 
14 #include <soc_common.h>
15 
arch_irq_enable(unsigned int irq)16 void arch_irq_enable(unsigned int irq)
17 {
18 	if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
19 		ite_intc_irq_enable(irq);
20 	}
21 }
22 
arch_irq_disable(unsigned int irq)23 void arch_irq_disable(unsigned int irq)
24 {
25 	if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
26 		ite_intc_irq_disable(irq);
27 	}
28 };
29 
arch_irq_is_enabled(unsigned int irq)30 int arch_irq_is_enabled(unsigned int irq)
31 {
32 	/*
33 	 * Return true from arch_irq_is_enabled() when external interrupt-enable
34 	 * bit, and SOC's IER are both true.
35 	 */
36 	if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
37 		return ((csr_read(mie) & BIT(IRQ_M_EXT)) &&
38 			ite_intc_irq_is_enable(irq));
39 	} else {
40 		return 0;
41 	}
42 }
43