1 /* 2 * Copyright (c) 2020 Intel Corporation 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 /* 6 * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. 7 * 8 * Functions here are designed to produce efficient code to 9 * search an Xtensa bitmask of interrupts, inspecting only those bits 10 * declared to be associated with a given interrupt level. Each 11 * dispatcher will handle exactly one flagged interrupt, in numerical 12 * order (low bits first) and will return a mask of that bit that can 13 * then be cleared by the calling code. Unrecognized bits for the 14 * level will invoke an error handler. 15 */ 16 17 #include <xtensa/config/core-isa.h> 18 #include <zephyr/sys/util.h> 19 #include <zephyr/sw_isr_table.h> 20 21 #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 22 #error core-isa.h interrupt level does not match dispatcher! 23 #endif 24 #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 25 #error core-isa.h interrupt level does not match dispatcher! 26 #endif 27 #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 28 #error core-isa.h interrupt level does not match dispatcher! 29 #endif 30 #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 31 #error core-isa.h interrupt level does not match dispatcher! 32 #endif 33 #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2 34 #error core-isa.h interrupt level does not match dispatcher! 35 #endif 36 #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2 37 #error core-isa.h interrupt level does not match dispatcher! 38 #endif 39 #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2 40 #error core-isa.h interrupt level does not match dispatcher! 41 #endif 42 #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2 43 #error core-isa.h interrupt level does not match dispatcher! 44 #endif 45 #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 3 46 #error core-isa.h interrupt level does not match dispatcher! 47 #endif 48 #if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3 49 #error core-isa.h interrupt level does not match dispatcher! 50 #endif 51 #if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3 52 #error core-isa.h interrupt level does not match dispatcher! 53 #endif 54 #if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 55 #error core-isa.h interrupt level does not match dispatcher! 56 #endif 57 #if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4 58 #error core-isa.h interrupt level does not match dispatcher! 59 #endif 60 #if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 4 61 #error core-isa.h interrupt level does not match dispatcher! 62 #endif 63 #if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 4 64 #error core-isa.h interrupt level does not match dispatcher! 65 #endif 66 #if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 5 67 #error core-isa.h interrupt level does not match dispatcher! 68 #endif 69 #if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5 70 #error core-isa.h interrupt level does not match dispatcher! 71 #endif 72 #if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 5 73 #error core-isa.h interrupt level does not match dispatcher! 74 #endif 75 #if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 5 76 #error core-isa.h interrupt level does not match dispatcher! 77 #endif 78 #if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 5 79 #error core-isa.h interrupt level does not match dispatcher! 80 #endif 81 #if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 7 82 #error core-isa.h interrupt level does not match dispatcher! 83 #endif 84 _xtensa_handle_one_int1(unsigned int mask)85static inline int _xtensa_handle_one_int1(unsigned int mask) 86 { 87 int irq; 88 89 if (mask & 0x3) { 90 if (mask & BIT(0)) { 91 mask = BIT(0); 92 irq = 0; 93 goto handle_irq; 94 } 95 if (mask & BIT(1)) { 96 mask = BIT(1); 97 irq = 1; 98 goto handle_irq; 99 } 100 } else { 101 if (mask & BIT(2)) { 102 mask = BIT(2); 103 irq = 2; 104 goto handle_irq; 105 } 106 if (mask & BIT(3)) { 107 mask = BIT(3); 108 irq = 3; 109 goto handle_irq; 110 } 111 } 112 return 0; 113 handle_irq: 114 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 115 return mask; 116 } 117 _xtensa_handle_one_int2(unsigned int mask)118static inline int _xtensa_handle_one_int2(unsigned int mask) 119 { 120 int irq; 121 122 if (mask & 0x30) { 123 if (mask & BIT(4)) { 124 mask = BIT(4); 125 irq = 4; 126 goto handle_irq; 127 } 128 if (mask & BIT(5)) { 129 mask = BIT(5); 130 irq = 5; 131 goto handle_irq; 132 } 133 } else { 134 if (mask & BIT(6)) { 135 mask = BIT(6); 136 irq = 6; 137 goto handle_irq; 138 } 139 if (mask & BIT(7)) { 140 mask = BIT(7); 141 irq = 7; 142 goto handle_irq; 143 } 144 } 145 return 0; 146 handle_irq: 147 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 148 return mask; 149 } 150 _xtensa_handle_one_int3(unsigned int mask)151static inline int _xtensa_handle_one_int3(unsigned int mask) 152 { 153 int irq; 154 155 if (mask & 0x300) { 156 if (mask & BIT(8)) { 157 mask = BIT(8); 158 irq = 8; 159 goto handle_irq; 160 } 161 if (mask & BIT(9)) { 162 mask = BIT(9); 163 irq = 9; 164 goto handle_irq; 165 } 166 } else { 167 if (mask & BIT(10)) { 168 mask = BIT(10); 169 irq = 10; 170 goto handle_irq; 171 } 172 if (mask & BIT(11)) { 173 mask = BIT(11); 174 irq = 11; 175 goto handle_irq; 176 } 177 } 178 return 0; 179 handle_irq: 180 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 181 return mask; 182 } 183 _xtensa_handle_one_int4(unsigned int mask)184static inline int _xtensa_handle_one_int4(unsigned int mask) 185 { 186 int irq; 187 188 if (mask & BIT(12)) { 189 mask = BIT(12); 190 irq = 12; 191 goto handle_irq; 192 } 193 if (mask & BIT(13)) { 194 mask = BIT(13); 195 irq = 13; 196 goto handle_irq; 197 } 198 if (mask & BIT(14)) { 199 mask = BIT(14); 200 irq = 14; 201 goto handle_irq; 202 } 203 return 0; 204 handle_irq: 205 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 206 return mask; 207 } 208 _xtensa_handle_one_int5(unsigned int mask)209static inline int _xtensa_handle_one_int5(unsigned int mask) 210 { 211 int irq; 212 213 if (mask & 0x18000) { 214 if (mask & BIT(15)) { 215 mask = BIT(15); 216 irq = 15; 217 goto handle_irq; 218 } 219 if (mask & BIT(16)) { 220 mask = BIT(16); 221 irq = 16; 222 goto handle_irq; 223 } 224 } else { 225 if (mask & BIT(17)) { 226 mask = BIT(17); 227 irq = 17; 228 goto handle_irq; 229 } 230 if (mask & BIT(18)) { 231 mask = BIT(18); 232 irq = 18; 233 goto handle_irq; 234 } 235 if (mask & BIT(19)) { 236 mask = BIT(19); 237 irq = 19; 238 goto handle_irq; 239 } 240 } 241 return 0; 242 handle_irq: 243 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 244 return mask; 245 } 246 _xtensa_handle_one_int7(unsigned int mask)247static inline int _xtensa_handle_one_int7(unsigned int mask) 248 { 249 int irq; 250 251 if (mask & BIT(20)) { 252 mask = BIT(20); 253 irq = 20; 254 goto handle_irq; 255 } 256 return 0; 257 handle_irq: 258 _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); 259 return mask; 260 } 261 _xtensa_handle_one_int0(unsigned int mask)262static inline int _xtensa_handle_one_int0(unsigned int mask) 263 { 264 return 0; 265 } _xtensa_handle_one_int6(unsigned int mask)266static inline int _xtensa_handle_one_int6(unsigned int mask) 267 { 268 return 0; 269 } 270
