1 /* 2 * Copyright (c) 2023 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <stdint.h> 8 9 #include <xtensa/config/core-isa.h> 10 11 #include <zephyr/devicetree.h> 12 #include <zephyr/arch/xtensa/xtensa_mmu.h> 13 #include <zephyr/sys/util.h> 14 15 const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = { 16 { 17 .start = (uint32_t)XCHAL_VECBASE_RESET_VADDR, 18 .end = (uint32_t)CONFIG_SRAM_OFFSET, 19 .attrs = XTENSA_MMU_PERM_X | XTENSA_MMU_CACHED_WB | XTENSA_MMU_MAP_SHARED, 20 .name = "vecbase", 21 }, 22 { 23 /* The ROM is 32MB but the address wraps around back to 0x00000000. 24 * So just skip the last page so we don't have to deal with integer 25 * overflow. 26 */ 27 .start = (uint32_t)DT_REG_ADDR(DT_NODELABEL(rom0)), 28 .end = (uint32_t)DT_REG_ADDR(DT_NODELABEL(rom0)) + 29 (uint32_t)DT_REG_SIZE(DT_NODELABEL(rom0)), 30 .attrs = XTENSA_MMU_PERM_X | XTENSA_MMU_CACHED_WB, 31 .name = "rom", 32 }, 33 }; 34 35 int xtensa_soc_mmu_ranges_num = ARRAY_SIZE(xtensa_soc_mmu_ranges); 36