1 /*
2 * Copyright (c) 2016 Piotr Mienkowski
3 * Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /** @file
8 * @brief Atmel SAM V71 MCU initialization code
9 *
10 * This file provides routines to initialize and support board-level hardware
11 * for the Atmel SAM V71 MCU.
12 */
13
14 #include <zephyr/kernel.h>
15 #include <zephyr/device.h>
16 #include <zephyr/init.h>
17 #include <zephyr/cache.h>
18 #include <zephyr/arch/cache.h>
19 #include <soc.h>
20 #include <cmsis_core.h>
21 #include <zephyr/logging/log.h>
22
23 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
24 LOG_MODULE_REGISTER(soc);
25
26 /**
27 * @brief Setup various clocks on SoC at boot time.
28 *
29 * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
30 * It is assumed that the relevant registers are at their reset value.
31 */
clock_init(void)32 static ALWAYS_INLINE void clock_init(void)
33 {
34 /* Switch the main clock to the internal OSC with 12MHz */
35 soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
36
37 /* Switch MCK (Master Clock) to the main clock */
38 soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
39
40 EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE;
41
42 soc_pmc_enable_clock_failure_detector();
43
44 if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
45 soc_supc_slow_clock_select_crystal_osc();
46 }
47
48
49 if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
50 /*
51 * Setup main external crystal oscillator.
52 */
53
54 /* We select maximum setup time.
55 * While start up time could be shortened
56 * this optimization is not deemed
57 * critical now.
58 */
59 soc_pmc_switch_mainck_to_xtal(false, 0xff);
60 }
61
62 /*
63 * Set FWS (Flash Wait State) value before increasing Master Clock
64 * (MCK) frequency.
65 * TODO: set FWS based on the actual MCK frequency and VDDIO value
66 * rather than maximum supported 150 MHz at standard VDDIO=2.7V
67 */
68 EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
69
70 /*
71 * Setup PLLA
72 */
73
74 /*
75 * PLL clock = Main * (MULA + 1) / DIVA
76 *
77 * By default, MULA == 24, DIVA == 1.
78 * With main crystal running at 12 MHz,
79 * PLL = 12 * (24 + 1) / 1 = 300 MHz
80 *
81 * With Processor Clock prescaler at 1
82 * Processor Clock (HCLK)=300 MHz.
83 */
84 soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
85 CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
86
87
88 soc_pmc_enable_upllck(0x3Fu);
89
90 /*
91 * Final setup of the Master Clock
92 */
93
94 /* Setting PLLA as MCK, first prescaler, then divider and source last */
95 soc_pmc_mck_set_prescaler(1);
96 soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV);
97 soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
98
99 /* Disable internal fast RC if we have an external crystal oscillator */
100 if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
101 soc_pmc_osc_disable_fastrc();
102 }
103 }
104
z_arm_platform_init(void)105 void z_arm_platform_init(void)
106 {
107 if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
108 /*
109 * Instruct CPU to enter Wait mode instead of Sleep mode to
110 * keep Processor Clock (HCLK) and thus be able to debug
111 * CPU using JTAG.
112 */
113 soc_pmc_enable_waitmode();
114 }
115
116 /*
117 * DTCM is enabled by default at reset, therefore we have to disable
118 * it first to get the caches into a state where then the
119 * sys_cache*-functions can enable them, if requested by the
120 * configuration.
121 */
122 SCB_InvalidateDCache();
123 SCB_DisableDCache();
124
125 /*
126 * Enable the caches only if configured to do so.
127 */
128 sys_cache_instr_enable();
129 sys_cache_data_enable();
130
131 /* Setup system clocks */
132 clock_init();
133 }
134
135 /**
136 * @brief Perform basic hardware initialization at boot.
137 *
138 * This needs to be run at the very beginning.
139 * So the init priority has to be 0 (zero).
140 *
141 * @return 0
142 */
atmel_samv71_init(void)143 static int atmel_samv71_init(void)
144 {
145 /* Check that the CHIP CIDR matches the HAL one */
146 if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
147 LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
148 (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
149 }
150
151 return 0;
152 }
153
154 SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0);
155
